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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_ram_4k.vhd] - Diff between revs 244 and 251

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Rev 244 Rev 251
Line 60... Line 60...
  Address_WPR                : ADDRESS_TYPE := x"1000";
  Address_WPR                : ADDRESS_TYPE := x"1000";
  Address_RAM                : ADDRESS_TYPE
  Address_RAM                : ADDRESS_TYPE
);
);
port(
port(
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Rd_Data                    : out DATA_TYPE
  Rd_Data                    : out DATA_TYPE;
 
  Write_Fault                : out std_logic
);
);
end entity;
end entity;
 
 
architecture behave of o8_ram_4k is
architecture behave of o8_ram_4k is
 
 
Line 113... Line 114...
  signal RAM_Wr_En_d         : std_logic := '0';
  signal RAM_Wr_En_d         : std_logic := '0';
  signal RAM_Rd_En_d         : std_logic := '0';
  signal RAM_Rd_En_d         : std_logic := '0';
  signal RAM_Rd_En_q         : std_logic := '0';
  signal RAM_Rd_En_q         : std_logic := '0';
  signal RAM_Rd_Data         : DATA_TYPE := OPEN8_NULLBUS;
  signal RAM_Rd_Data         : DATA_TYPE := OPEN8_NULLBUS;
 
 
 
  signal Write_Fault_d       : std_logic := '0';
 
 
begin
begin
 
 
Write_Protect_On : if( Write_Protect )generate
Write_Protect_On : if( Write_Protect )generate
 
 
  WPR_Addr_Match             <= '1' when WPR_Comp_Addr = WPR_User_Addr else '0';
  WPR_Addr_Match             <= '1' when WPR_Comp_Addr = WPR_User_Addr else '0';
Line 129... Line 132...
                                ISR_En;
                                ISR_En;
 
 
  RAM_Rd_En_d                <= RAM_Addr_Match and Rd_En;
  RAM_Rd_En_d                <= RAM_Addr_Match and Rd_En;
  RAM_Wr_En_d                <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
  RAM_Wr_En_d                <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
 
 
 
  Write_Fault_d              <= RAM_Addr_Match and (not RAM_Region_Match) and Wr_En;
 
 
  RAM_proc: process( Reset, Clock )
  RAM_proc: process( Reset, Clock )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
 
 
      WPR_Reg_Sel_q          <= (others => '0');
      WPR_Reg_Sel_q          <= (others => '0');
Line 143... Line 148...
 
 
      Write_Mask             <= Default_Mask;
      Write_Mask             <= Default_Mask;
 
 
      RAM_Rd_En_q            <= '0';
      RAM_Rd_En_q            <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
 
 
 
      Write_Fault            <= '0';
 
 
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      WPR_Reg_Sel_q          <= WPR_Reg_Sel_d;
      WPR_Reg_Sel_q          <= WPR_Reg_Sel_d;
 
 
      WPR_Wr_En_q            <= WPR_Wr_En_d;
      WPR_Wr_En_q            <= WPR_Wr_En_d;
      WPR_Wr_Data_q          <= Wr_Data_d;
      WPR_Wr_Data_q          <= Wr_Data_d;
Line 183... Line 191...
            Rd_Data          <= Write_Mask_3;
            Rd_Data          <= Write_Mask_3;
          when others =>
          when others =>
            null;
            null;
        end case;
        end case;
      end if;
      end if;
 
 
 
      Write_Fault            <= Write_Fault_d;
 
 
    end if;
    end if;
  end process;
  end process;
 
 
end generate;
end generate;
 
 

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