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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_register.vhd] - Diff between revs 180 and 191

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Rev 180 Rev 191
Line 92... Line 92...
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Wr_En             <= '0';
      Wr_En             <= '0';
      Wr_Data_q         <= (others => '0');
      Wr_Data_q         <= (others => '0');
      Reg_Out           <= Default_Value;
      Reg_Out           <= Default_Value;
      Rd_En             <= '0';
      Rd_En             <= '0';
      Rd_Data           <= x"00";
      Rd_Data           <= OPEN8_NULLBUS;
    elsif( rising_edge( Clock ) )then
    elsif( rising_edge( Clock ) )then
      Wr_En             <= Addr_Match and Wr_Enable;
      Wr_En             <= Addr_Match and Wr_Enable;
      Wr_Data_q         <= Wr_Data;
      Wr_Data_q         <= Wr_Data;
      if( Wr_En = '1' )then
      if( Wr_En = '1' )then
        Reg_Out         <= Wr_Data_q;
        Reg_Out         <= Wr_Data_q;
      end if;
      end if;
 
 
      Rd_Data           <= (others => '0');
      Rd_Data           <= OPEN8_NULLBUS;
      Rd_En             <= Addr_Match and Rd_Enable;
      Rd_En             <= Addr_Match and Rd_Enable;
      if( Rd_En = '1' )then
      if( Rd_En = '1' )then
        Rd_Data         <= Reg_Out;
        Rd_Data         <= Reg_Out;
      end if;
      end if;
 
 

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