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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_register.vhd] - Diff between revs 180 and 191
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| Rev 180 |
Rev 191 |
| Line 92... |
Line 92... |
if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Wr_En <= '0';
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Wr_En <= '0';
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Wr_Data_q <= (others => '0');
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Wr_Data_q <= (others => '0');
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Reg_Out <= Default_Value;
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Reg_Out <= Default_Value;
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= x"00";
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_Data_q <= Wr_Data;
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Wr_Data_q <= Wr_Data;
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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Reg_Out <= Wr_Data_q;
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Reg_Out <= Wr_Data_q;
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end if;
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end if;
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_En <= Addr_Match and Rd_Enable;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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Rd_Data <= Reg_Out;
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Rd_Data <= Reg_Out;
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end if;
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end if;
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