OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_register.vhd] - Diff between revs 194 and 213

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 194 Rev 213
Line 20... Line 20... 
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
--
 
--
 
-- VHDL Units :  o8_register
 
-- VHDL Units :  o8_register
 
-- Description:  Provides a single addressible 8-bit register
 
-- Description:  Provides a single addressible 8-bit output register
 
--
 
--
 
-- Register Map:
 
-- Register Map:
 
-- Offset  Bitfield Description                        Read/Write
 
-- Offset  Bitfield Description                        Read/Write
 
--   0x00  AAAAAAAA Registered Outputs                    (RW)
 
--   0x00  AAAAAAAA Registered Outputs                    (RW)
 
--
 
--

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.