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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_register.vhd] - Diff between revs 213 and 217
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| Rev 213 |
Rev 217 |
| Line 62... |
Line 62... |
);
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);
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end entity;
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end entity;
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architecture behave of o8_register is
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architecture behave of o8_register is
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function ceil_log2 (x : in natural) return natural is
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variable retval : natural;
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begin
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retval := 1;
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while ((2**retval) - 1) < x loop
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retval := retval + 1;
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end loop;
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return retval;
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end function;
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constant User_Addr : std_logic_vector(15 downto 0)
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constant User_Addr : std_logic_vector(15 downto 0)
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:= Address(15 downto 0);
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:= Address(15 downto 0);
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alias Comp_Addr is Bus_Address(15 downto 0);
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alias Comp_Addr is Bus_Address(15 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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signal Wr_En : std_logic;
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signal Wr_En : std_logic;
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