URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_register.vhd] - Diff between revs 217 and 221
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 217 |
Rev 221 |
| Line 79... |
Line 79... |
|
|
io_reg: process( Clock, Reset )
|
io_reg: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Wr_En <= '0';
|
Wr_En <= '0';
|
Wr_Data_q <= (others => '0');
|
Wr_Data_q <= x"00";
|
Reg_Out <= Default_Value;
|
Reg_Out <= Default_Value;
|
Rd_En <= '0';
|
Rd_En <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_En <= Addr_Match and Wr_Enable;
|
| Line 95... |
Line 95... |
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Addr_Match and Rd_Enable;
|
Rd_En <= Addr_Match and Rd_Enable;
|
if( Rd_En = '1' )then
|
if( Rd_En = '1' )then
|
Rd_Data <= Reg_Out;
|
Rd_Data <= Reg_Out;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
Register_Out <= Reg_Out;
|
Register_Out <= Reg_Out;
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.