| Line 31... |
Line 31... |
-- Revision History
|
-- Revision History
|
-- Author Date Change
|
-- Author Date Change
|
------------------ -------- ---------------------------------------------------
|
------------------ -------- ---------------------------------------------------
|
-- Seth Henry 12/20/19 Design Start
|
-- Seth Henry 12/20/19 Design Start
|
-- Seth Henry 04/16/20 Modified to use Open8 bus record
|
-- Seth Henry 04/16/20 Modified to use Open8 bus record
|
|
-- Seth Henry 05/18/20 Added write qualification input
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
| Line 48... |
Line 49... |
Default_Value : DATA_TYPE := x"00";
|
Default_Value : DATA_TYPE := x"00";
|
Address : ADDRESS_TYPE
|
Address : ADDRESS_TYPE
|
);
|
);
|
port(
|
port(
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
|
Write_Qual : in std_logic := '1';
|
Rd_Data : out DATA_TYPE;
|
Rd_Data : out DATA_TYPE;
|
--
|
--
|
Register_Out : out DATA_TYPE
|
Register_Out : out DATA_TYPE
|
);
|
);
|
end entity;
|
end entity;
|
| Line 63... |
Line 65... |
|
|
constant User_Addr : std_logic_vector(15 downto 0)
|
constant User_Addr : std_logic_vector(15 downto 0)
|
:= Address(15 downto 0);
|
:= Address(15 downto 0);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
|
signal Addr_Match : std_logic;
|
signal Addr_Match : std_logic;
|
signal Wr_En : std_logic;
|
|
signal Wr_Data_q : DATA_TYPE;
|
signal Wr_En_d : std_logic := '0';
|
signal Reg_Out : DATA_TYPE;
|
signal Wr_En_q : std_logic := '0';
|
signal Rd_En : std_logic;
|
alias Wr_Data_d is Open8_Bus.Wr_Data;
|
|
signal Wr_Data_q : DATA_TYPE := x"00";
|
|
signal Rd_En_d : std_logic := '0';
|
|
signal Rd_En_q : std_logic := '0';
|
|
|
|
signal Reg_Out : DATA_TYPE := x"00";
|
|
|
begin
|
begin
|
|
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
|
|
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
|
|
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
|
|
|
io_reg: process( Clock, Reset )
|
io_reg: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Wr_En <= '0';
|
Wr_En_q <= '0';
|
Wr_Data_q <= x"00";
|
Wr_Data_q <= x"00";
|
Reg_Out <= Default_Value;
|
Reg_Out <= Default_Value;
|
Rd_En <= '0';
|
Rd_En_q <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
|
Wr_En_q <= Wr_En_d;
|
Wr_Data_q <= Open8_Bus.Wr_Data;
|
Wr_Data_q <= Wr_Data_d;
|
if( Wr_En = '1' )then
|
if( Wr_En_q = '1' and Write_Qual = '1' )then
|
Reg_Out <= Wr_Data_q;
|
Reg_Out <= Wr_Data_q;
|
end if;
|
end if;
|
|
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
|
Rd_En_q <= Rd_En_d;
|
if( Rd_En = '1' )then
|
if( Rd_En_q = '1' )then
|
Rd_Data <= Reg_Out;
|
Rd_Data <= Reg_Out;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
