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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_register_wide.vhd] - Diff between revs 279 and 297
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| Rev 279 |
Rev 297 |
| Line 24... |
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-- VHDL Units : o8_register_wide
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-- VHDL Units : o8_register_wide
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-- Description: Provides a single addressible 16-bit output register
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-- Description: Provides a single addressible 16-bit output register
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA Registered Outputs (RW)
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-- 0x00 AAAAAAAA Registered Output 0 (RW)
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-- 0x01 AAAAAAAA Registered Output 1 (RW)
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-- 0x02 AAAAAAAA Registered Output 2 (RW)
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-- 0x03 AAAAAAAA Registered Output 3 (RW)
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 05/24/20 Design copied and modified from o8_register
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-- Seth Henry 05/24/20 Design copied and modified from o8_register
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