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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rom_32k.vhd] - Diff between revs 174 and 191
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| Rev 174 |
Rev 191 |
| Line 52... |
Line 52... |
constant User_Addr : std_logic_vector(15 downto 15) :=
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constant User_Addr : std_logic_vector(15 downto 15) :=
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Address(15 downto 15);
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Address(15 downto 15);
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alias Comp_Addr is Bus_Address(15 downto 15);
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alias Comp_Addr is Bus_Address(15 downto 15);
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alias ROM_Addr is Bus_Address(14 downto 0);
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alias ROM_Addr is Bus_Address(14 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic := '0';
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signal Rd_En : std_logic;
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signal Rd_En : std_logic := '0';
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signal Rd_Data_i : DATA_TYPE;
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signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
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begin
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begin
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-- Note that this RAM should be created without an output FF (unregistered Q)
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-- Note that this RAM should be created without an output FF (unregistered Q)
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U_ROM_CORE : entity work.rom_32k_core
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U_ROM_CORE : entity work.rom_32k_core
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| Line 72... |
Line 72... |
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RAM_proc: process( Reset, Clock )
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RAM_proc: process( Reset, Clock )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Rd_En <= Addr_Match;
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Rd_En <= Addr_Match;
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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Rd_Data <= Rd_Data_i;
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Rd_Data <= Rd_Data_i;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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