URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rom_32k.vhd] - Diff between revs 217 and 223
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 217 |
Rev 223 |
| Line 39... |
Line 39... |
);
|
);
|
port(
|
port(
|
Clock : in std_logic;
|
Clock : in std_logic;
|
Reset : in std_logic;
|
Reset : in std_logic;
|
--
|
--
|
Bus_Address : in ADDRESS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Rd_Enable : in std_logic;
|
|
Rd_Data : out DATA_TYPE
|
Rd_Data : out DATA_TYPE
|
);
|
);
|
end entity;
|
end entity;
|
|
|
architecture behave of o8_rom_32k is
|
architecture behave of o8_rom_32k is
|
|
|
constant User_Addr : std_logic_vector(15 downto 15) :=
|
constant User_Addr : std_logic_vector(15 downto 15) :=
|
Address(15 downto 15);
|
Address(15 downto 15);
|
alias Comp_Addr is Bus_Address(15 downto 15);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 15);
|
alias ROM_Addr is Bus_Address(14 downto 0);
|
alias ROM_Addr is Open8_Bus.Address(14 downto 0);
|
|
|
signal Addr_Match : std_logic := '0';
|
signal Addr_Match : std_logic := '0';
|
signal Rd_En : std_logic := '0';
|
signal Rd_En : std_logic := '0';
|
signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
|
signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
|
|
|
| Line 66... |
Line 65... |
address => ROM_Addr,
|
address => ROM_Addr,
|
clock => Clock,
|
clock => Clock,
|
q => Rd_Data_i
|
q => Rd_Data_i
|
);
|
);
|
|
|
Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
|
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
|
|
'0';
|
|
|
RAM_proc: process( Reset, Clock )
|
RAM_proc: process( Reset, Clock )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Rd_En <= '0';
|
Rd_En <= '0';
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.