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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rtc.vhd] - Diff between revs 224 and 244

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Rev 224 Rev 244
Line 45... Line 45...
--
--
-- Revision History
-- Revision History
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      04/16/20 Revision block added
-- Seth Henry      04/16/20 Revision block added
 
-- Seth Henry      05/18/20 Added write qualification input
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_arith.all;
Line 61... Line 62...
generic(
generic(
  Address                    : ADDRESS_TYPE
  Address                    : ADDRESS_TYPE
);
);
port(
port(
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
 
  Write_Qual                 : in  std_logic := '1';
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
  --
  --
  Interrupt_PIT              : out std_logic;
  Interrupt_PIT              : out std_logic;
  Interrupt_RTC              : out std_logic
  Interrupt_RTC              : out std_logic
);
);
Line 74... Line 76...
 
 
  alias Clock                is Open8_Bus.Clock;
  alias Clock                is Open8_Bus.Clock;
  alias Reset                is Open8_Bus.Reset;
  alias Reset                is Open8_Bus.Reset;
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
 
 
  constant User_Addr         : std_logic_vector(15 downto 3)
  constant User_Addr         : std_logic_vector(15 downto 3) :=
                               := Address(15 downto 3);
                                Address(15 downto 3);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 3);
 
  signal Addr_Match          : std_logic;
 
 
 
  alias  Reg_Addr            is Open8_Bus.Address(2 downto 0);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 3);
  signal Reg_Addr_q          : std_logic_vector(2 downto 0);
  signal Addr_Match          : std_logic := '0';
 
 
  signal Wr_En               : std_logic;
  alias  Reg_Sel_d           is Open8_Bus.Address(2 downto 0);
  signal Wr_Data_q           : DATA_TYPE;
  signal Reg_Sel_q           : std_logic_vector(2 downto 0) := (others => '0');
  signal Rd_En               : std_logic;
  signal Wr_En_d             : std_logic := '0';
 
  signal Wr_En_q             : std_logic := '0';
 
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
 
  signal Wr_Data_q           : DATA_TYPE := x"00";
 
  signal Rd_En_d             : std_logic := '0';
 
  signal Rd_En_q             : std_logic := '0';
 
 
  type PIT_TYPE is record
  type PIT_TYPE is record
    timer_cnt                : DATA_TYPE;
    timer_cnt                : DATA_TYPE;
    timer_ro                 : std_logic;
    timer_ro                 : std_logic;
  end record;
  end record;
Line 145... Line 150...
  signal update_ctmr         : std_logic_vector(3 downto 0);
  signal update_ctmr         : std_logic_vector(3 downto 0);
 
 
begin
begin
 
 
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
 
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
 
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
 
 
  Interrupt_PIT              <= pit.timer_ro;
  Interrupt_PIT              <= pit.timer_ro;
  Interrupt_RTC              <= rtc.frac_ro;
  Interrupt_RTC              <= rtc.frac_ro;
 
 
  io_reg: process( Clock, Reset )
  io_reg: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
 
      Reg_Sel_q              <= "000";
 
      Wr_En_q                <= '0';
 
      Wr_Data_q              <= x"00";
 
      Rd_En_q                <= '0';
 
      Rd_Data                <= OPEN8_NULLBUS;
 
 
      pit.timer_cnt          <= x"00";
      pit.timer_cnt          <= x"00";
      pit.timer_ro           <= '0';
      pit.timer_ro           <= '0';
 
 
      rtc.frac               <= DECISEC;
      rtc.frac               <= DECISEC;
      rtc.frac_ro            <= '0';
      rtc.frac_ro            <= '0';
Line 197... Line 210...
      update_ctmr            <= (others => '0');
      update_ctmr            <= (others => '0');
 
 
      interval               <= x"00";
      interval               <= x"00";
      update_interval        <= '0';
      update_interval        <= '0';
 
 
      Wr_Data_q              <= (others => '0');
 
      Reg_Addr_q             <= (others => '0');
 
      Wr_En                  <= '0';
 
      Rd_En                  <= '0';
 
      Rd_Data                <= OPEN8_NULLBUS;
 
 
 
    elsif( rising_edge( Clock ) )then
    elsif( rising_edge( Clock ) )then
 
 
      -- Periodic Interval Timer
      -- Periodic Interval Timer
      pit.timer_cnt          <= pit.timer_cnt - uSec_Tick;
      pit.timer_cnt          <= pit.timer_cnt - uSec_Tick;
      pit.timer_ro           <= '0';
      pit.timer_ro           <= '0';
Line 327... Line 334...
        update_shd           <= '0';
        update_shd           <= '0';
      end if;
      end if;
 
 
      update_interval        <= '0';
      update_interval        <= '0';
 
 
      Reg_Addr_q             <= Reg_Addr;
      Reg_Sel_q              <= Reg_Sel_d;
      Wr_Data_q              <= Open8_Bus.Wr_Data;
 
 
      Wr_En_q                <= Wr_En_d;
 
      Wr_Data_q              <= Wr_Data_d;
 
 
      Wr_En                  <= Addr_Match and Open8_Bus.Wr_En;
 
      update_rtc             <= '0';
      update_rtc             <= '0';
      if( Wr_En = '1' )then
      if( Wr_En_q = '1' )then
        case( Reg_Addr_q )is
        case( Reg_Sel_q )is
          when "000" =>
          when "000" =>
            interval         <= Wr_Data_q;
            interval         <= Wr_Data_q;
            update_interval  <= '1';
            update_interval  <= '1';
 
 
          when "001" =>
          when "001" =>
Line 371... Line 379...
      update_ctmr            <= update_ctmr - or_reduce(update_ctmr);
      update_ctmr            <= update_ctmr - or_reduce(update_ctmr);
      if( rtc.frac_ro = '1' )then
      if( rtc.frac_ro = '1' )then
        update_ctmr          <= (others => '1');
        update_ctmr          <= (others => '1');
      end if;
      end if;
 
 
 
      Rd_En_q                <= Rd_En_d;
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_En                  <= Addr_Match and Open8_Bus.Rd_En;
      if( Rd_En_q = '1' )then
      if( Rd_En = '1' )then
        case( Reg_Sel_q )is
        case( Reg_Addr_q )is
 
          when "000" =>
          when "000" =>
            Rd_Data          <= interval;
            Rd_Data          <= interval;
          when "001" =>
          when "001" =>
            Rd_Data          <= shd_tens;
            Rd_Data          <= shd_tens;
          when "010" =>
          when "010" =>

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