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-- Copyright (c)2013 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units : realtime_clock
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-- VHDL Units : realtime_clock
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-- Description: Provides automatically updated registers that maintain the
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-- Description: Provides automatically updated registers that maintain the
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-- : time of day. Keeps track of the day of week, hours, minutes
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-- : time of day. Keeps track of the day of week, hours, minutes
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-- : seconds, and tenths of a second. Module is doubled buffered
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-- : seconds, and tenths of a second. Module is doubled buffered
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-- : to ensure time consistency during accesses. Also provides
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-- : to ensure time consistency during accesses. Also provides
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Line 82... |
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signal uSec_Cntr : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )
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signal uSec_Cntr : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )
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:= (others => '0');
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:= (others => '0');
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signal uSec_Tick_i : std_logic;
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signal uSec_Tick_i : std_logic;
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signal interval : DATA_TYPE;
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type PIT_TYPE is record
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signal timer_cnt : DATA_TYPE;
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timer_cnt : DATA_TYPE;
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signal timer_ro : std_logic;
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timer_ro : std_logic;
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end record;
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signal pit : PIT_TYPE;
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type RTC_TYPE is record
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frac : std_logic_vector(15 downto 0);
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frac_ro : std_logic;
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tens_l : std_logic_vector(3 downto 0);
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tens_l_ro : std_logic;
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signal rtc_frac : std_logic_vector(15 downto 0);
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tens_u : std_logic_vector(3 downto 0);
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signal frac_ro : std_logic;
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tens_u_ro : std_logic;
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signal rtc_tens : DATA_TYPE;
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secs_l : std_logic_vector(3 downto 0);
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signal tens_ro : std_logic;
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secs_l_ro : std_logic;
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signal rtc_secs : DATA_TYPE;
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secs_u : std_logic_vector(3 downto 0);
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signal secs_ro : std_logic;
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secs_u_ro : std_logic;
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signal rtc_mins : DATA_TYPE;
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mins_l : std_logic_vector(3 downto 0);
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signal mins_ro : std_logic;
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mins_l_ro : std_logic;
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signal rtc_hours : DATA_TYPE;
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mins_u : std_logic_vector(3 downto 0);
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signal hours_ro : std_logic;
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mins_u_ro : std_logic;
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signal rtc_dow : DATA_TYPE;
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hours_l : std_logic_vector(3 downto 0);
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hours_l_ro : std_logic;
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hours_u : std_logic_vector(3 downto 0);
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hours_u_ro : std_logic;
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dow : std_logic_vector(2 downto 0);
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end record;
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constant DECISEC : std_logic_vector(15 downto 0) :=
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conv_std_logic_vector(10000,16);
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signal rtc : RTC_TYPE;
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signal interval : DATA_TYPE;
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signal shd_tens : DATA_TYPE;
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signal shd_tens : DATA_TYPE;
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signal shd_secs : DATA_TYPE;
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signal shd_secs : DATA_TYPE;
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signal shd_mins : DATA_TYPE;
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signal shd_mins : DATA_TYPE;
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signal shd_hours : DATA_TYPE;
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signal shd_hours : DATA_TYPE;
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begin
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begin
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uSec_Tick <= uSec_Tick_i;
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uSec_Tick <= uSec_Tick_i;
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Interrupt_PIT <= timer_ro;
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Interrupt_PIT <= pit.timer_ro;
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Interrupt_RTC <= frac_ro;
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Interrupt_RTC <= rtc.frac_ro;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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uSec_Cntr <= (others => '0');
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uSec_Cntr <= (others => '0');
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uSec_Tick_i <= '0';
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uSec_Tick_i <= '0';
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interval <= x"00";
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pit.timer_cnt <= x"00";
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timer_cnt <= x"00";
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pit.timer_ro <= '0';
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timer_ro <= '0';
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rtc.frac <= DECISEC;
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rtc.frac_ro <= '0';
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rtc.tens_l <= (others => '0');
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rtc.tens_l_ro <= '0';
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rtc_frac <= (others => '0');
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rtc.tens_u <= (others => '0');
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frac_ro <= '0';
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rtc.tens_u_ro <= '0';
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rtc_tens <= (others => '0');
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rtc.secs_l <= (others => '0');
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tens_ro <= '0';
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rtc.secs_l_ro <= '0';
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rtc_secs <= (others => '0');
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rtc.secs_u <= (others => '0');
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secs_ro <= '0';
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rtc.secs_u_ro <= '0';
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rtc_mins <= (others => '0');
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rtc.mins_l <= (others => '0');
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mins_ro <= '0';
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rtc.mins_l_ro <= '0';
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rtc_hours <= (others => '0');
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rtc.mins_u <= (others => '0');
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hours_ro <= '0';
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rtc.mins_u_ro <= '0';
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rtc_dow <= (others => '0');
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rtc.hours_l <= (others => '0');
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rtc.hours_l_ro <= '0';
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rtc.hours_u <= (others => '0');
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rtc.hours_u_ro <= '0';
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rtc.dow <= (others => '0');
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shd_tens <= (others => '0');
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shd_tens <= (others => '0');
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shd_secs <= (others => '0');
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shd_secs <= (others => '0');
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shd_mins <= (others => '0');
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shd_mins <= (others => '0');
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shd_hours <= (others => '0');
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shd_hours <= (others => '0');
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Line 193... |
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update_rtc <= '0';
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update_rtc <= '0';
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update_shd <= '0';
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update_shd <= '0';
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update_ctmr <= (others => '0');
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update_ctmr <= (others => '0');
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interval <= x"00";
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Wr_Data_q <= (others => '0');
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Wr_Data_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
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Wr_En <= '0';
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Wr_En <= '0';
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= x"00";
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Rd_Data <= x"00";
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if( uSec_Cntr = 0 )then
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if( uSec_Cntr = 0 )then
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uSec_Cntr <= DLY_1USEC;
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uSec_Cntr <= DLY_1USEC;
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uSec_Tick_i <= or_reduce(Interval);
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uSec_Tick_i <= or_reduce(Interval);
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end if;
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end if;
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timer_ro <= '0';
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pit.timer_ro <= '0';
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frac_ro <= '0';
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tens_ro <= '0';
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rtc.frac_ro <= '0';
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secs_ro <= '0';
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rtc.tens_l_ro <= '0';
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mins_ro <= '0';
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rtc.tens_u_ro <= '0';
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hours_ro <= '0';
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rtc.secs_l_ro <= '0';
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rtc.secs_u_ro <= '0';
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rtc.mins_l_ro <= '0';
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rtc.mins_u_ro <= '0';
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rtc.hours_l_ro <= '0';
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rtc.hours_u_ro <= '0';
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-- Periodic Interval Timer
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-- Periodic Interval Timer
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timer_cnt <= timer_cnt - uSec_Tick_i;
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pit.timer_cnt <= pit.timer_cnt - uSec_Tick_i;
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if( or_reduce(timer_cnt) = '0' )then
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if( or_reduce(pit.timer_cnt) = '0' )then
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timer_cnt <= interval;
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pit.timer_cnt <= interval;
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timer_ro <= or_reduce(interval); -- Only issue output on Int > 0
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pit.timer_ro <= or_reduce(interval); -- Only issue output on Int > 0
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end if;
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end if;
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-- Fractional decisecond counter - cycles every 10k microseconds
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-- Fractional decisecond counter - cycles every 10k microseconds
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rtc_frac <= rtc_frac - uSec_Tick_i;
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rtc.frac <= rtc.frac - uSec_Tick_i;
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if( or_reduce(rtc_frac) = '0' or update_rtc = '1' )then
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if( or_reduce(rtc.frac) = '0' or update_rtc = '1' )then
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rtc_frac <= x"2710";
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rtc.frac <= DECISEC;
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frac_ro <= not update_rtc;
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rtc.frac_ro <= not update_rtc;
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end if;
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end if;
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-- Decisecond counter
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-- Decisecond counter (lower)
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rtc_tens <= rtc_tens + frac_ro;
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rtc.tens_l <= rtc.tens_l + rtc.frac_ro;
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if( update_rtc = '1' )then
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if( update_rtc = '1' )then
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rtc_tens <= shd_tens;
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rtc.tens_l <= shd_tens(3 downto 0);
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elsif( rtc_tens = x"64")then
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elsif( rtc.tens_l > x"9")then
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rtc_tens <= (others => '0');
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rtc.tens_l <= (others => '0');
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tens_ro <= '1';
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rtc.tens_l_ro <= '1';
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end if;
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end if;
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-- Second counter
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-- Decisecond counter (upper)
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rtc_secs <= rtc_secs + tens_ro;
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rtc.tens_u <= rtc.tens_u + rtc.tens_l_ro;
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if( update_rtc = '1' )then
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if( update_rtc = '1' )then
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rtc_secs <= shd_secs;
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rtc.tens_u <= shd_tens(7 downto 4);
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elsif( rtc_secs = x"3C")then
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elsif( rtc.tens_u > x"9")then
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rtc_secs <= (others => '0');
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rtc.tens_u <= (others => '0');
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secs_ro <= '1';
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rtc.tens_u_ro <= '1';
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end if;
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end if;
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-- Minute counter
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-- Second counter (lower)
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rtc_mins <= rtc_mins + secs_ro;
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rtc.secs_l <= rtc.secs_l + rtc.tens_u_ro;
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if( update_rtc = '1' )then
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if( update_rtc = '1' )then
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rtc_mins <= shd_mins;
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rtc.secs_l <= shd_secs(3 downto 0);
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elsif( rtc_mins = x"3C")then
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elsif( rtc.secs_l > x"9")then
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rtc_mins <= (others => '0');
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rtc.secs_l <= (others => '0');
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mins_ro <= '1';
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rtc.secs_l_ro <= '1';
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end if;
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end if;
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-- Hour counter
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-- Second counter (upper)
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rtc_hours <= rtc_hours + mins_ro;
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rtc.secs_u <= rtc.secs_u + rtc.secs_l_ro;
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if( update_rtc = '1' )then
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if( update_rtc = '1' )then
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rtc_hours <= shd_hours;
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rtc.secs_u <= shd_secs(7 downto 4);
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elsif( rtc_hours = x"18")then
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elsif( rtc.secs_u > x"5")then
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rtc_hours <= (others => '0');
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rtc.secs_u <= (others => '0');
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hours_ro <= '1';
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rtc.secs_u_ro <= '1';
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end if;
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end if;
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-- Day of Week counter
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-- Minutes counter (lower)
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rtc_dow <= rtc_dow + hours_ro;
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rtc.mins_l <= rtc.mins_l + rtc.secs_u_ro;
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if( update_rtc = '1' )then
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if( update_rtc = '1' )then
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rtc_dow <= shd_dow;
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rtc.mins_l <= shd_mins(3 downto 0);
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elsif( rtc_dow = x"07")then
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elsif( rtc.mins_l > x"9")then
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rtc_dow <= (others => '0');
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rtc.mins_l <= (others => '0');
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rtc.mins_l_ro <= '1';
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end if;
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end if;
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-- Coherency timer - ensures that the shadow registers are updated with
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-- Minutes counter (upper)
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-- valid time data by delaying updates until the rtc registers have
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rtc.mins_u <= rtc.mins_u + rtc.mins_l_ro;
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-- finished cascading.
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if( update_rtc = '1' )then
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update_rtc <= '0';
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rtc.mins_u <= shd_mins(7 downto 4);
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update_ctmr <= update_ctmr - or_reduce(update_ctmr);
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elsif( rtc.mins_u > x"5")then
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if( frac_ro = '1' )then
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rtc.mins_u <= (others => '0');
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update_ctmr <= x"9";
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rtc.mins_u_ro <= '1';
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end if;
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-- Hour counter (lower)
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rtc.hours_l <= rtc.hours_l + rtc.mins_u_ro;
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if( update_rtc = '1' )then
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rtc.hours_l <= shd_hours(3 downto 0);
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elsif( rtc.hours_l > x"9")then
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rtc.hours_l <= (others => '0');
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rtc.hours_l_ro <= '1';
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end if;
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-- Hour counter (upper)
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rtc.hours_u <= rtc.hours_u + rtc.hours_l_ro;
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if( update_rtc = '1' )then
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rtc.hours_u <= shd_hours(7 downto 4);
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end if;
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if( rtc.hours_u >= x"2" and rtc.hours_l > x"3" )then
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rtc.hours_l <= (others => '0');
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rtc.hours_u <= (others => '0');
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rtc.hours_u_ro <= '1';
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end if;
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-- Day of Week counter
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rtc.dow <= rtc.dow + rtc.hours_u_ro;
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if( update_rtc = '1' )then
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rtc.dow <= shd_dow(2 downto 0);
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elsif( rtc.dow = x"07")then
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rtc.dow <= (others => '0');
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end if;
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end if;
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-- Copy the RTC registers to the shadow registers when the coherency
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-- Copy the RTC registers to the shadow registers when the coherency
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-- timer is zero (RTC registers are static)
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-- timer is zero (RTC registers are static)
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if( update_shd = '1' and or_reduce(update_ctmr) = '0' )then
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if( update_shd = '1' and or_reduce(update_ctmr) = '0' )then
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shd_tens <= rtc_tens;
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shd_tens <= rtc.tens_u & rtc.tens_l;
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shd_secs <= rtc_secs;
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shd_secs <= rtc.secs_u & rtc.secs_l;
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shd_mins <= rtc_mins;
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shd_mins <= rtc.mins_u & rtc.mins_l;
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shd_hours <= rtc_hours;
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shd_hours <= rtc.hours_u & rtc.hours_l;
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shd_dow <= rtc_dow;
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shd_dow <= "00000" & rtc.dow;
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update_shd <= '0';
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update_shd <= '0';
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end if;
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end if;
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Reg_Addr_q <= Reg_Addr;
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Reg_Addr_q <= Reg_Addr;
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Wr_Data_q <= Wr_Data;
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Wr_Data_q <= Wr_Data;
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_En <= Addr_Match and Wr_Enable;
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update_rtc <= '0';
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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case( Reg_Addr_q )is
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case( Reg_Addr_q )is
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when "000" =>
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when "000" =>
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interval <= Wr_Data_q;
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interval <= Wr_Data_q;
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when "001" =>
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when "001" =>
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shd_tens <= '0' & Wr_Data_q(6 downto 0);
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shd_tens <= Wr_Data_q;
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when "010" =>
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when "010" =>
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shd_secs <= "00" & Wr_Data_q(5 downto 0);
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shd_secs <= Wr_Data_q;
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when "011" =>
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when "011" =>
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shd_mins <= "00" & Wr_Data_q(5 downto 0);
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shd_mins <= Wr_Data_q;
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when "100" =>
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when "100" =>
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shd_hours <= "000" & Wr_Data_q(4 downto 0);
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shd_hours <= Wr_Data_q;
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when "101" =>
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when "101" =>
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shd_dow <= "00000" & Wr_Data_q(2 downto 0);
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shd_dow <= Wr_Data_q;
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when "110" =>
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when "110" =>
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update_rtc <= '1';
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update_rtc <= '1';
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when "111" =>
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when "111" =>
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update_shd <= '1';
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update_shd <= '1';
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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-- Coherency timer - ensures that the shadow registers are updated with
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-- valid time data by delaying updates until the rtc registers have
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-- finished cascading.
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update_ctmr <= update_ctmr - or_reduce(update_ctmr);
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if( rtc.frac_ro = '1' )then
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update_ctmr <= (others => '1');
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end if;
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Rd_Data <= (others => '0');
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Rd_Data <= (others => '0');
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_En <= Addr_Match and Rd_Enable;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Addr_q )is
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case( Reg_Addr_q )is
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when "000" =>
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when "000" =>
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| Line 344... |
Line 401... |
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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