| Line 7... |
Line 7... |
-- : tick for external use.
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-- : tick for external use.
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x0 AAAAAAAA Periodic Interval Timer in uS (RW)
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-- 0x0 AAAAAAAA Periodic Interval Timer in uS (RW)
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-- 0x1 -AAAAAAA Tenths (0x00 - 0x99) (RW)
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-- 0x1 -AAAAAAA Tenths (0x00 - 0x63) (RW)
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-- 0x2 --AAAAAA Seconds (0x00 - 0x59) (RW)
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-- 0x2 --AAAAAA Seconds (0x00 - 0x3B) (RW)
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-- 0x3 --AAAAAA Minutes (0x00 - 0x59) (RW)
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-- 0x3 --AAAAAA Minutes (0x00 - 0x3B) (RW)
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-- 0x4 ---AAAAA Hours (0x00 - 0x23) (RW)
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-- 0x4 ---AAAAA Hours (0x00 - 0x17) (RW)
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-- 0x5 -----AAA Day of Week (0x00 - 0x06) (RW)
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-- 0x5 -----AAA Day of Week (0x00 - 0x06) (RW)
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-- 0x6 -------- Update RTC regs from Shadow Regs (WO)
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-- 0x6 -------- Update RTC regs from Shadow Regs (WO)
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-- 0x7 A------- Update Shadow Regs from RTC regs (RW)
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-- 0x7 A------- Update Shadow Regs from RTC regs (RW)
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-- A = Update is Busy
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-- A = Update is Busy
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--
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-- Note that values are stored in packed BCD, not hex
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 30... |
Line 27... |
library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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|
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entity o8_rtc is
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entity o8_rtc is
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generic(
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generic(
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Address : ADDRESS_TYPE;
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Sys_Freq : real;
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Reset_Level : std_logic;
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Reset_Level : std_logic;
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Sys_Freq : real
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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uSec_Tick : out std_logic;
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uSec_Tick : out std_logic;
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| Line 52... |
Line 49... |
);
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);
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end entity;
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end entity;
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|
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architecture behave of o8_rtc is
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architecture behave of o8_rtc is
|
|
|
-- The ceil_log2 function returns the minimum register width required to
|
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-- hold the supplied integer.
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function ceil_log2 (x : in natural) return natural is
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variable retval : natural;
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begin
|
|
retval := 1;
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while ((2**retval) - 1) < x loop
|
|
retval := retval + 1;
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end loop;
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return retval;
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end ceil_log2;
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|
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constant User_Addr : std_logic_vector(15 downto 3)
|
constant User_Addr : std_logic_vector(15 downto 3)
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:= Address(15 downto 3);
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:= Address(15 downto 3);
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alias Comp_Addr is Bus_Address(15 downto 3);
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alias Comp_Addr is Bus_Address(15 downto 3);
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signal Addr_Match : std_logic;
|
signal Addr_Match : std_logic;
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|
|
| Line 210... |
Line 195... |
|
|
uSec_Cntr <= uSec_Cntr - 1;
|
uSec_Cntr <= uSec_Cntr - 1;
|
uSec_Tick_i <= '0';
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uSec_Tick_i <= '0';
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if( uSec_Cntr = 0 )then
|
if( uSec_Cntr = 0 )then
|
uSec_Cntr <= DLY_1USEC;
|
uSec_Cntr <= DLY_1USEC;
|
uSec_Tick_i <= '1';
|
uSec_Tick_i <= or_reduce(Interval);
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end if;
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end if;
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|
|
pit.timer_ro <= '0';
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pit.timer_ro <= '0';
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|
|
rtc.frac_ro <= '0';
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rtc.frac_ro <= '0';
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