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-- VHDL Units : realtime_clock
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-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units : o8_rtc
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-- Description: Provides automatically updated registers that maintain the
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-- Description: Provides automatically updated registers that maintain the
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-- : time of day. Keeps track of the day of week, hours, minutes
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-- : time of day. Keeps track of the day of week, hours, minutes
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-- : seconds, and tenths of a second. Module is doubled buffered
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-- : seconds, and tenths of a second. Module is doubled buffered
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-- : to ensure time consistency during accesses. Also provides
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-- : to ensure time consistency during accesses. Also provides
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-- : a programmable periodic interrupt timer, as well as a uSec
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-- : a programmable periodic interrupt timer, as well as a uSec
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Wr_Data_q <= (others => '0');
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Wr_Data_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
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Wr_En <= '0';
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Wr_En <= '0';
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= x"00";
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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uSec_Cntr <= uSec_Cntr - 1;
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uSec_Cntr <= uSec_Cntr - 1;
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uSec_Tick_i <= '0';
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uSec_Tick_i <= '0';
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update_ctmr <= update_ctmr - or_reduce(update_ctmr);
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update_ctmr <= update_ctmr - or_reduce(update_ctmr);
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if( rtc.frac_ro = '1' )then
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if( rtc.frac_ro = '1' )then
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update_ctmr <= (others => '1');
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update_ctmr <= (others => '1');
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end if;
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end if;
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_En <= Addr_Match and Rd_Enable;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Addr_q )is
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case( Reg_Addr_q )is
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when "000" =>
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when "000" =>
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Rd_Data <= interval;
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Rd_Data <= interval;
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