| Line 137... |
Line 137... |
conv_std_logic_vector(10000,16);
|
conv_std_logic_vector(10000,16);
|
|
|
signal rtc : RTC_TYPE;
|
signal rtc : RTC_TYPE;
|
|
|
signal interval : DATA_TYPE;
|
signal interval : DATA_TYPE;
|
|
signal mask_pit_int : std_logic;
|
|
|
signal shd_tens : DATA_TYPE;
|
signal shd_tens : DATA_TYPE;
|
signal shd_secs : DATA_TYPE;
|
signal shd_secs : DATA_TYPE;
|
signal shd_mins : DATA_TYPE;
|
signal shd_mins : DATA_TYPE;
|
signal shd_hours : DATA_TYPE;
|
signal shd_hours : DATA_TYPE;
|
| Line 205... |
Line 206... |
update_rtc <= '0';
|
update_rtc <= '0';
|
update_shd <= '0';
|
update_shd <= '0';
|
update_ctmr <= (others => '0');
|
update_ctmr <= (others => '0');
|
|
|
interval <= x"00";
|
interval <= x"00";
|
|
mask_pit_int <= '0';
|
|
|
Wr_Data_q <= (others => '0');
|
Wr_Data_q <= (others => '0');
|
Reg_Addr_q <= (others => '0');
|
Reg_Addr_q <= (others => '0');
|
Wr_En <= '0';
|
Wr_En <= '0';
|
Rd_En <= '0';
|
Rd_En <= '0';
|
| Line 226... |
Line 228... |
-- Periodic Interval Timer
|
-- Periodic Interval Timer
|
pit.timer_cnt <= pit.timer_cnt - uSec_Tick_i;
|
pit.timer_cnt <= pit.timer_cnt - uSec_Tick_i;
|
pit.timer_ro <= '0';
|
pit.timer_ro <= '0';
|
if( or_reduce(pit.timer_cnt) = '0' )then
|
if( or_reduce(pit.timer_cnt) = '0' )then
|
pit.timer_cnt <= interval;
|
pit.timer_cnt <= interval;
|
pit.timer_ro <= or_reduce(interval); -- Only issue output on Int > 0
|
pit.timer_ro <= or_reduce(interval) and -- Only issue output on Int > 0
|
|
(not mask_pit_int); -- and we didn't just update it
|
|
|
end if;
|
end if;
|
|
|
-- Fractional decisecond counter - cycles every 10k microseconds
|
-- Fractional decisecond counter - cycles every 10k microseconds
|
rtc.frac <= rtc.frac - uSec_Tick_i;
|
rtc.frac <= rtc.frac - uSec_Tick_i;
|
rtc.frac_ro <= '0';
|
rtc.frac_ro <= '0';
|
| Line 339... |
Line 343... |
shd_hours <= rtc.hours_u & rtc.hours_l;
|
shd_hours <= rtc.hours_u & rtc.hours_l;
|
shd_dow <= "00000" & rtc.dow;
|
shd_dow <= "00000" & rtc.dow;
|
update_shd <= '0';
|
update_shd <= '0';
|
end if;
|
end if;
|
|
|
|
mask_pit_int <= '0';
|
|
|
Reg_Addr_q <= Reg_Addr;
|
Reg_Addr_q <= Reg_Addr;
|
Wr_Data_q <= Wr_Data;
|
Wr_Data_q <= Wr_Data;
|
|
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_En <= Addr_Match and Wr_Enable;
|
update_rtc <= '0';
|
update_rtc <= '0';
|
if( Wr_En = '1' )then
|
if( Wr_En = '1' )then
|
case( Reg_Addr_q )is
|
case( Reg_Addr_q )is
|
when "000" =>
|
when "000" =>
|
interval <= Wr_Data_q;
|
interval <= Wr_Data_q;
|
|
mask_pit_int <= '1';
|
|
|
when "001" =>
|
when "001" =>
|
shd_tens <= Wr_Data_q;
|
shd_tens <= Wr_Data_q;
|
|
|
when "010" =>
|
when "010" =>
|
