OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rtc.vhd] - Diff between revs 209 and 210

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 209 Rev 210
Line 137... Line 137...
                           conv_std_logic_vector(10000,16);
                           conv_std_logic_vector(10000,16);
 
 
  signal rtc            : RTC_TYPE;
  signal rtc            : RTC_TYPE;
 
 
  signal interval       : DATA_TYPE;
  signal interval       : DATA_TYPE;
  signal mask_pit_int   : std_logic;
  signal update_interval: std_logic;
 
  signal new_interval   : DATA_TYPE;
 
 
  signal shd_tens       : DATA_TYPE;
  signal shd_tens       : DATA_TYPE;
  signal shd_secs       : DATA_TYPE;
  signal shd_secs       : DATA_TYPE;
  signal shd_mins       : DATA_TYPE;
  signal shd_mins       : DATA_TYPE;
  signal shd_hours      : DATA_TYPE;
  signal shd_hours      : DATA_TYPE;
Line 206... Line 207...
      update_rtc        <= '0';
      update_rtc        <= '0';
      update_shd        <= '0';
      update_shd        <= '0';
      update_ctmr       <= (others => '0');
      update_ctmr       <= (others => '0');
 
 
      interval          <= x"00";
      interval          <= x"00";
      mask_pit_int      <= '0';
      update_interval        <= '0';
 
      new_interval           <= x"00";
 
 
      Wr_Data_q         <= (others => '0');
      Wr_Data_q         <= (others => '0');
      Reg_Addr_q        <= (others => '0');
      Reg_Addr_q        <= (others => '0');
      Wr_En             <= '0';
      Wr_En             <= '0';
      Rd_En             <= '0';
      Rd_En             <= '0';
Line 226... Line 228...
      end if;
      end if;
 
 
      -- Periodic Interval Timer
      -- Periodic Interval Timer
      pit.timer_cnt     <= pit.timer_cnt - uSec_Tick_i;
      pit.timer_cnt     <= pit.timer_cnt - uSec_Tick_i;
      pit.timer_ro      <= '0';
      pit.timer_ro      <= '0';
      if( or_reduce(pit.timer_cnt) = '0' )then
      if( update_interval = '1' )then
 
        pit.timer_cnt        <= new_interval;
 
      elsif( or_reduce(pit.timer_cnt) = '0' )then
        pit.timer_cnt   <= interval;
        pit.timer_cnt   <= interval;
        pit.timer_ro    <= or_reduce(interval) and -- Only issue output on Int > 0
        pit.timer_ro         <= or_reduce(interval);
                           (not mask_pit_int);     -- and we didn't just update it
 
 
 
      end if;
      end if;
 
 
      -- Fractional decisecond counter - cycles every 10k microseconds
      -- Fractional decisecond counter - cycles every 10k microseconds
      rtc.frac          <= rtc.frac - uSec_Tick_i;
      rtc.frac          <= rtc.frac - uSec_Tick_i;
Line 343... Line 346...
        shd_hours       <= rtc.hours_u & rtc.hours_l;
        shd_hours       <= rtc.hours_u & rtc.hours_l;
        shd_dow         <= "00000" & rtc.dow;
        shd_dow         <= "00000" & rtc.dow;
        update_shd      <= '0';
        update_shd      <= '0';
      end if;
      end if;
 
 
      mask_pit_int      <= '0';
      update_interval        <= '0';
 
 
      Reg_Addr_q        <= Reg_Addr;
      Reg_Addr_q        <= Reg_Addr;
      Wr_Data_q         <= Wr_Data;
      Wr_Data_q         <= Wr_Data;
 
 
      Wr_En             <= Addr_Match and Wr_Enable;
      Wr_En             <= Addr_Match and Wr_Enable;
      update_rtc        <= '0';
      update_rtc        <= '0';
      if( Wr_En = '1' )then
      if( Wr_En = '1' )then
        case( Reg_Addr_q )is
        case( Reg_Addr_q )is
          when "000" =>
          when "000" =>
            interval    <= Wr_Data_q;
            new_interval     <= Wr_Data_q;
            mask_pit_int <= '1';
            update_interval  <= '1';
 
 
          when "001" =>
          when "001" =>
            shd_tens    <= Wr_Data_q;
            shd_tens    <= Wr_Data_q;
 
 
          when "010" =>
          when "010" =>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.