| Line 137... |
Line 137... |
conv_std_logic_vector(10000,16);
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conv_std_logic_vector(10000,16);
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signal rtc : RTC_TYPE;
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signal rtc : RTC_TYPE;
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signal interval : DATA_TYPE;
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signal interval : DATA_TYPE;
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signal mask_pit_int : std_logic;
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signal update_interval: std_logic;
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signal new_interval : DATA_TYPE;
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signal shd_tens : DATA_TYPE;
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signal shd_tens : DATA_TYPE;
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signal shd_secs : DATA_TYPE;
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signal shd_secs : DATA_TYPE;
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signal shd_mins : DATA_TYPE;
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signal shd_mins : DATA_TYPE;
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signal shd_hours : DATA_TYPE;
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signal shd_hours : DATA_TYPE;
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| Line 206... |
Line 207... |
update_rtc <= '0';
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update_rtc <= '0';
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update_shd <= '0';
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update_shd <= '0';
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update_ctmr <= (others => '0');
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update_ctmr <= (others => '0');
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interval <= x"00";
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interval <= x"00";
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mask_pit_int <= '0';
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update_interval <= '0';
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new_interval <= x"00";
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Wr_Data_q <= (others => '0');
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Wr_Data_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
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Wr_En <= '0';
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Wr_En <= '0';
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Rd_En <= '0';
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Rd_En <= '0';
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| Line 226... |
Line 228... |
end if;
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end if;
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-- Periodic Interval Timer
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-- Periodic Interval Timer
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pit.timer_cnt <= pit.timer_cnt - uSec_Tick_i;
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pit.timer_cnt <= pit.timer_cnt - uSec_Tick_i;
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pit.timer_ro <= '0';
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pit.timer_ro <= '0';
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if( or_reduce(pit.timer_cnt) = '0' )then
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if( update_interval = '1' )then
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pit.timer_cnt <= new_interval;
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elsif( or_reduce(pit.timer_cnt) = '0' )then
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pit.timer_cnt <= interval;
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pit.timer_cnt <= interval;
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pit.timer_ro <= or_reduce(interval) and -- Only issue output on Int > 0
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pit.timer_ro <= or_reduce(interval);
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(not mask_pit_int); -- and we didn't just update it
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end if;
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end if;
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-- Fractional decisecond counter - cycles every 10k microseconds
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-- Fractional decisecond counter - cycles every 10k microseconds
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rtc.frac <= rtc.frac - uSec_Tick_i;
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rtc.frac <= rtc.frac - uSec_Tick_i;
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| Line 343... |
Line 346... |
shd_hours <= rtc.hours_u & rtc.hours_l;
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shd_hours <= rtc.hours_u & rtc.hours_l;
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shd_dow <= "00000" & rtc.dow;
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shd_dow <= "00000" & rtc.dow;
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update_shd <= '0';
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update_shd <= '0';
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end if;
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end if;
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mask_pit_int <= '0';
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update_interval <= '0';
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Reg_Addr_q <= Reg_Addr;
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Reg_Addr_q <= Reg_Addr;
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Wr_Data_q <= Wr_Data;
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Wr_Data_q <= Wr_Data;
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_En <= Addr_Match and Wr_Enable;
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update_rtc <= '0';
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update_rtc <= '0';
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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case( Reg_Addr_q )is
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case( Reg_Addr_q )is
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when "000" =>
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when "000" =>
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interval <= Wr_Data_q;
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new_interval <= Wr_Data_q;
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mask_pit_int <= '1';
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update_interval <= '1';
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when "001" =>
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when "001" =>
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shd_tens <= Wr_Data_q;
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shd_tens <= Wr_Data_q;
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when "010" =>
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when "010" =>
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