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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rtc.vhd] - Diff between revs 210 and 211

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Rev 210	Rev 211
Line 138...	Line 138...

`signal rtc : RTC_TYPE;`	`signal rtc : RTC_TYPE;`

`signal interval : DATA_TYPE;`	`signal interval : DATA_TYPE;`
`signal update_interval: std_logic;`	`signal update_interval: std_logic;`
`signal new_interval : DATA_TYPE;`

`signal shd_tens : DATA_TYPE;`	`signal shd_tens : DATA_TYPE;`
`signal shd_secs : DATA_TYPE;`	`signal shd_secs : DATA_TYPE;`
`signal shd_mins : DATA_TYPE;`	`signal shd_mins : DATA_TYPE;`
`signal shd_hours : DATA_TYPE;`	`signal shd_hours : DATA_TYPE;`
Line 208...	Line 207...
`update_shd <= '0';`	`update_shd <= '0';`
`update_ctmr <= (others => '0');`	`update_ctmr <= (others => '0');`

`interval <= x"00";`	`interval <= x"00";`
`update_interval <= '0';`	`update_interval <= '0';`
`new_interval <= x"00";`

`Wr_Data_q <= (others => '0');`	`Wr_Data_q <= (others => '0');`
`Reg_Addr_q <= (others => '0');`	`Reg_Addr_q <= (others => '0');`
`Wr_En <= '0';`	`Wr_En <= '0';`
`Rd_En <= '0';`	`Rd_En <= '0';`
Line 229...	Line 227...

`-- Periodic Interval Timer`	`-- Periodic Interval Timer`
`pit.timer_cnt <= pit.timer_cnt - uSec_Tick_i;`	`pit.timer_cnt <= pit.timer_cnt - uSec_Tick_i;`
`pit.timer_ro <= '0';`	`pit.timer_ro <= '0';`
`if( update_interval = '1' )then`	`if( update_interval = '1' )then`
`pit.timer_cnt <= new_interval;`	`pit.timer_cnt <= interval;`
`elsif( or_reduce(pit.timer_cnt) = '0' )then`	`elsif( or_reduce(pit.timer_cnt) = '0' )then`
`pit.timer_cnt <= interval;`	`pit.timer_cnt <= interval;`
`pit.timer_ro <= or_reduce(interval);`	`pit.timer_ro <= or_reduce(interval);`

`end if;`	`end if;`

`-- Fractional decisecond counter - cycles every 10k microseconds`	`-- Fractional decisecond counter - cycles every 10k microseconds`
`rtc.frac <= rtc.frac - uSec_Tick_i;`	`rtc.frac <= rtc.frac - uSec_Tick_i;`
`rtc.frac_ro <= '0';`	`rtc.frac_ro <= '0';`
Line 356...	Line 353...
`Wr_En <= Addr_Match and Wr_Enable;`	`Wr_En <= Addr_Match and Wr_Enable;`
`update_rtc <= '0';`	`update_rtc <= '0';`
`if( Wr_En = '1' )then`	`if( Wr_En = '1' )then`
`case( Reg_Addr_q )is`	`case( Reg_Addr_q )is`
`when "000" =>`	`when "000" =>`
`new_interval <= Wr_Data_q;`	`interval <= Wr_Data_q;`
`update_interval <= '1';`	`update_interval <= '1';`

`when "001" =>`	`when "001" =>`
`shd_tens <= Wr_Data_q;`	`shd_tens <= Wr_Data_q;`

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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rtc.vhd] - Diff between revs 210 and 211