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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rtc.vhd] - Diff between revs 217 and 223

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Rev 217	Rev 223
Line 61...	Line 61...
`port(`	`port(`
`Clock : in std_logic;`	`Clock : in std_logic;`
`Reset : in std_logic;`	`Reset : in std_logic;`
`uSec_Tick : out std_logic;`	`uSec_Tick : out std_logic;`
`--`	`--`
`Bus_Address : in ADDRESS_TYPE;`	`Open8_Bus : in OPEN8_BUS_TYPE;`
`Wr_Enable : in std_logic;`
`Wr_Data : in DATA_TYPE;`
`Rd_Enable : in std_logic;`
`Rd_Data : out DATA_TYPE;`	`Rd_Data : out DATA_TYPE;`
`--`	`--`
`Interrupt_PIT : out std_logic;`	`Interrupt_PIT : out std_logic;`
`Interrupt_RTC : out std_logic`	`Interrupt_RTC : out std_logic`
`);`	`);`
Line 76...	Line 73...

`architecture behave of o8_rtc is`	`architecture behave of o8_rtc is`

`constant User_Addr : std_logic_vector(15 downto 3)`	`constant User_Addr : std_logic_vector(15 downto 3)`
`:= Address(15 downto 3);`	`:= Address(15 downto 3);`
`alias Comp_Addr is Bus_Address(15 downto 3);`	`alias Comp_Addr is Open8_Bus.Address(15 downto 3);`
`signal Addr_Match : std_logic;`	`signal Addr_Match : std_logic;`

`alias Reg_Addr is Bus_Address(2 downto 0);`	`alias Reg_Addr is Open8_Bus.Address(2 downto 0);`
`signal Reg_Addr_q : std_logic_vector(2 downto 0);`	`signal Reg_Addr_q : std_logic_vector(2 downto 0);`

`signal Wr_En : std_logic;`	`signal Wr_En : std_logic;`
`signal Wr_Data_q : DATA_TYPE;`	`signal Wr_Data_q : DATA_TYPE;`
`signal Rd_En : std_logic;`	`signal Rd_En : std_logic;`
Line 348...	Line 345...
`end if;`	`end if;`

`update_interval <= '0';`	`update_interval <= '0';`

`Reg_Addr_q <= Reg_Addr;`	`Reg_Addr_q <= Reg_Addr;`
`Wr_Data_q <= Wr_Data;`	`Wr_Data_q <= Open8_Bus.Wr_Data;`

`Wr_En <= Addr_Match and Wr_Enable;`	`Wr_En <= Addr_Match and Open8_Bus.Wr_En;`
`update_rtc <= '0';`	`update_rtc <= '0';`
`if( Wr_En = '1' )then`	`if( Wr_En = '1' )then`
`case( Reg_Addr_q )is`	`case( Reg_Addr_q )is`
`when "000" =>`	`when "000" =>`
`interval <= Wr_Data_q;`	`interval <= Wr_Data_q;`
Line 392...	Line 389...
`if( rtc.frac_ro = '1' )then`	`if( rtc.frac_ro = '1' )then`
`update_ctmr <= (others => '1');`	`update_ctmr <= (others => '1');`
`end if;`	`end if;`

`Rd_Data <= OPEN8_NULLBUS;`	`Rd_Data <= OPEN8_NULLBUS;`
`Rd_En <= Addr_Match and Rd_Enable;`	`Rd_En <= Addr_Match and Open8_Bus.Rd_En;`
`if( Rd_En = '1' )then`	`if( Rd_En = '1' )then`
`case( Reg_Addr_q )is`	`case( Reg_Addr_q )is`
`when "000" =>`	`when "000" =>`
`Rd_Data <= interval;`	`Rd_Data <= interval;`
`when "001" =>`	`when "001" =>`

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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rtc.vhd] - Diff between revs 217 and 223