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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rtc.vhd] - Diff between revs 223 and 224

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Rev 223 Rev 224
Line 40... Line 40...
--   0x4   --BBAAAA Hours   (0x00 - 0x23)              (RW)
--   0x4   --BBAAAA Hours   (0x00 - 0x23)              (RW)
--   0x5   -----AAA Day of Week (0x00 - 0x06)          (RW)
--   0x5   -----AAA Day of Week (0x00 - 0x06)          (RW)
--   0x6   -------- Update RTC regs from Shadow Regs   (WO)
--   0x6   -------- Update RTC regs from Shadow Regs   (WO)
--   0x7   A------- Update Shadow Regs from RTC regs   (RW)
--   0x7   A------- Update Shadow Regs from RTC regs   (RW)
--                  A = Update is Busy
--                  A = Update is Busy
 
--
 
-- Revision History
 
-- Author          Date     Change
 
------------------ -------- ---------------------------------------------------
 
-- Seth Henry      04/16/20 Revision block added
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_arith.all;
Line 52... Line 57...
library work;
library work;
  use work.open8_pkg.all;
  use work.open8_pkg.all;
 
 
entity o8_rtc is
entity o8_rtc is
generic(
generic(
  Sys_Freq                   : real;
 
  Reset_Level                : std_logic;
 
  Address                    : ADDRESS_TYPE
  Address                    : ADDRESS_TYPE
);
);
port(
port(
  Clock                      : in  std_logic;
 
  Reset                      : in  std_logic;
 
  uSec_Tick                  : out std_logic;
 
  --
 
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
  --
  --
  Interrupt_PIT              : out std_logic;
  Interrupt_PIT              : out std_logic;
  Interrupt_RTC              : out std_logic
  Interrupt_RTC              : out std_logic
);
);
end entity;
end entity;
 
 
architecture behave of o8_rtc is
architecture behave of o8_rtc is
 
 
 
  alias Clock                is Open8_Bus.Clock;
 
  alias Reset                is Open8_Bus.Reset;
 
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
 
 
  constant User_Addr         : std_logic_vector(15 downto 3)
  constant User_Addr         : std_logic_vector(15 downto 3)
                               := Address(15 downto 3);
                               := Address(15 downto 3);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 3);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 3);
  signal Addr_Match          : std_logic;
  signal Addr_Match          : std_logic;
 
 
Line 83... Line 86...
 
 
  signal Wr_En               : std_logic;
  signal Wr_En               : std_logic;
  signal Wr_Data_q           : DATA_TYPE;
  signal Wr_Data_q           : DATA_TYPE;
  signal Rd_En               : std_logic;
  signal Rd_En               : std_logic;
 
 
  constant DLY_1USEC_VAL     : integer := integer(Sys_Freq / 1000000.0);
 
  constant DLY_1USEC_WDT     : integer := ceil_log2(DLY_1USEC_VAL - 1);
 
  constant DLY_1USEC         : std_logic_vector :=
 
                     conv_std_logic_vector( DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
 
 
 
  signal uSec_Cntr           : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )
 
                               := (others => '0');
 
  signal uSec_Tick_i         : std_logic;
 
 
 
  type PIT_TYPE is record
  type PIT_TYPE is record
    timer_cnt                : DATA_TYPE;
    timer_cnt                : DATA_TYPE;
    timer_ro                 : std_logic;
    timer_ro                 : std_logic;
  end record;
  end record;
 
 
Line 150... Line 144...
  signal update_shd          : std_logic;
  signal update_shd          : std_logic;
  signal update_ctmr         : std_logic_vector(3 downto 0);
  signal update_ctmr         : std_logic_vector(3 downto 0);
 
 
begin
begin
 
 
  uSec_Tick                  <= uSec_Tick_i;
 
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
 
 
  Interrupt_PIT              <= pit.timer_ro;
  Interrupt_PIT              <= pit.timer_ro;
  Interrupt_RTC              <= rtc.frac_ro;
  Interrupt_RTC              <= rtc.frac_ro;
 
 
  io_reg: process( Clock, Reset )
  io_reg: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      uSec_Cntr              <= (others => '0');
 
      uSec_Tick_i            <= '0';
 
 
 
      pit.timer_cnt          <= x"00";
      pit.timer_cnt          <= x"00";
      pit.timer_ro           <= '0';
      pit.timer_ro           <= '0';
 
 
      rtc.frac               <= DECISEC;
      rtc.frac               <= DECISEC;
      rtc.frac_ro            <= '0';
      rtc.frac_ro            <= '0';
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      Rd_En                  <= '0';
      Rd_En                  <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
 
 
    elsif( rising_edge( Clock ) )then
    elsif( rising_edge( Clock ) )then
 
 
      uSec_Cntr              <= uSec_Cntr - 1;
 
      uSec_Tick_i            <= '0';
 
      if( uSec_Cntr = 0 )then
 
        uSec_Cntr            <= DLY_1USEC;
 
        uSec_Tick_i          <= '1';
 
      end if;
 
 
 
      -- Periodic Interval Timer
      -- Periodic Interval Timer
      pit.timer_cnt          <= pit.timer_cnt - uSec_Tick_i;
      pit.timer_cnt          <= pit.timer_cnt - uSec_Tick;
      pit.timer_ro           <= '0';
      pit.timer_ro           <= '0';
      if( update_interval = '1' )then
      if( update_interval = '1' )then
        pit.timer_cnt        <= interval;
        pit.timer_cnt        <= interval;
      elsif( or_reduce(pit.timer_cnt) = '0' )then
      elsif( or_reduce(pit.timer_cnt) = '0' )then
        pit.timer_cnt        <= interval;
        pit.timer_cnt        <= interval;
        pit.timer_ro         <= or_reduce(interval);
        pit.timer_ro         <= or_reduce(interval);
      end if;
      end if;
 
 
      -- Fractional decisecond counter - cycles every 10k microseconds
      -- Fractional decisecond counter - cycles every 10k microseconds
      rtc.frac               <= rtc.frac - uSec_Tick_i;
      rtc.frac               <= rtc.frac - uSec_Tick;
      rtc.frac_ro            <= '0';
      rtc.frac_ro            <= '0';
      if( or_reduce(rtc.frac) = '0' or update_rtc = '1' )then
      if( or_reduce(rtc.frac) = '0' or update_rtc = '1' )then
        rtc.frac             <= DECISEC;
        rtc.frac             <= DECISEC;
        rtc.frac_ro          <= not update_rtc;
        rtc.frac_ro          <= not update_rtc;
      end if;
      end if;

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