| Line 40... |
Line 40... |
-- 0x4 --BBAAAA Hours (0x00 - 0x23) (RW)
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-- 0x4 --BBAAAA Hours (0x00 - 0x23) (RW)
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-- 0x5 -----AAA Day of Week (0x00 - 0x06) (RW)
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-- 0x5 -----AAA Day of Week (0x00 - 0x06) (RW)
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-- 0x6 -------- Update RTC regs from Shadow Regs (WO)
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-- 0x6 -------- Update RTC regs from Shadow Regs (WO)
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-- 0x7 A------- Update Shadow Regs from RTC regs (RW)
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-- 0x7 A------- Update Shadow Regs from RTC regs (RW)
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-- A = Update is Busy
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-- A = Update is Busy
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/16/20 Revision block added
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 52... |
Line 57... |
library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_rtc is
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entity o8_rtc is
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generic(
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generic(
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Sys_Freq : real;
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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uSec_Tick : out std_logic;
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--
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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Interrupt_PIT : out std_logic;
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Interrupt_PIT : out std_logic;
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Interrupt_RTC : out std_logic
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Interrupt_RTC : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_rtc is
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architecture behave of o8_rtc is
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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constant User_Addr : std_logic_vector(15 downto 3)
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constant User_Addr : std_logic_vector(15 downto 3)
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:= Address(15 downto 3);
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:= Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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| Line 83... |
Line 86... |
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signal Wr_En : std_logic;
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signal Wr_En : std_logic;
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signal Wr_Data_q : DATA_TYPE;
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signal Wr_Data_q : DATA_TYPE;
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signal Rd_En : std_logic;
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signal Rd_En : std_logic;
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constant DLY_1USEC_VAL : integer := integer(Sys_Freq / 1000000.0);
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constant DLY_1USEC_WDT : integer := ceil_log2(DLY_1USEC_VAL - 1);
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constant DLY_1USEC : std_logic_vector :=
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conv_std_logic_vector( DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
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signal uSec_Cntr : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )
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:= (others => '0');
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signal uSec_Tick_i : std_logic;
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type PIT_TYPE is record
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type PIT_TYPE is record
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timer_cnt : DATA_TYPE;
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timer_cnt : DATA_TYPE;
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timer_ro : std_logic;
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timer_ro : std_logic;
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end record;
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end record;
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| Line 150... |
Line 144... |
signal update_shd : std_logic;
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signal update_shd : std_logic;
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signal update_ctmr : std_logic_vector(3 downto 0);
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signal update_ctmr : std_logic_vector(3 downto 0);
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|
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begin
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begin
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|
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uSec_Tick <= uSec_Tick_i;
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Interrupt_PIT <= pit.timer_ro;
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Interrupt_PIT <= pit.timer_ro;
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Interrupt_RTC <= rtc.frac_ro;
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Interrupt_RTC <= rtc.frac_ro;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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uSec_Cntr <= (others => '0');
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uSec_Tick_i <= '0';
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|
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pit.timer_cnt <= x"00";
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pit.timer_cnt <= x"00";
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pit.timer_ro <= '0';
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pit.timer_ro <= '0';
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rtc.frac <= DECISEC;
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rtc.frac <= DECISEC;
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rtc.frac_ro <= '0';
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rtc.frac_ro <= '0';
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| Line 215... |
Line 205... |
Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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|
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
|
|
|
uSec_Cntr <= uSec_Cntr - 1;
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uSec_Tick_i <= '0';
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if( uSec_Cntr = 0 )then
|
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uSec_Cntr <= DLY_1USEC;
|
|
uSec_Tick_i <= '1';
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end if;
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|
|
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-- Periodic Interval Timer
|
-- Periodic Interval Timer
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pit.timer_cnt <= pit.timer_cnt - uSec_Tick_i;
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pit.timer_cnt <= pit.timer_cnt - uSec_Tick;
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pit.timer_ro <= '0';
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pit.timer_ro <= '0';
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if( update_interval = '1' )then
|
if( update_interval = '1' )then
|
pit.timer_cnt <= interval;
|
pit.timer_cnt <= interval;
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elsif( or_reduce(pit.timer_cnt) = '0' )then
|
elsif( or_reduce(pit.timer_cnt) = '0' )then
|
pit.timer_cnt <= interval;
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pit.timer_cnt <= interval;
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pit.timer_ro <= or_reduce(interval);
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pit.timer_ro <= or_reduce(interval);
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end if;
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end if;
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|
|
-- Fractional decisecond counter - cycles every 10k microseconds
|
-- Fractional decisecond counter - cycles every 10k microseconds
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rtc.frac <= rtc.frac - uSec_Tick_i;
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rtc.frac <= rtc.frac - uSec_Tick;
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rtc.frac_ro <= '0';
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rtc.frac_ro <= '0';
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if( or_reduce(rtc.frac) = '0' or update_rtc = '1' )then
|
if( or_reduce(rtc.frac) = '0' or update_rtc = '1' )then
|
rtc.frac <= DECISEC;
|
rtc.frac <= DECISEC;
|
rtc.frac_ro <= not update_rtc;
|
rtc.frac_ro <= not update_rtc;
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end if;
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end if;
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