| Line 45... |
Line 45... |
--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/16/20 Revision block added
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-- Seth Henry 04/16/20 Revision block added
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-- Seth Henry 05/18/20 Added write qualification input
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 61... |
Line 62... |
generic(
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generic(
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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Interrupt_PIT : out std_logic;
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Interrupt_PIT : out std_logic;
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Interrupt_RTC : out std_logic
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Interrupt_RTC : out std_logic
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);
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);
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| Line 74... |
Line 76... |
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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constant User_Addr : std_logic_vector(15 downto 3)
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constant User_Addr : std_logic_vector(15 downto 3) :=
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:= Address(15 downto 3);
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Address(15 downto 3);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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signal Addr_Match : std_logic;
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alias Reg_Addr is Open8_Bus.Address(2 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 3);
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signal Reg_Addr_q : std_logic_vector(2 downto 0);
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signal Addr_Match : std_logic := '0';
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signal Wr_En : std_logic;
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alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
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signal Wr_Data_q : DATA_TYPE;
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signal Reg_Sel_q : std_logic_vector(2 downto 0) := (others => '0');
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signal Rd_En : std_logic;
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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type PIT_TYPE is record
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type PIT_TYPE is record
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timer_cnt : DATA_TYPE;
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timer_cnt : DATA_TYPE;
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timer_ro : std_logic;
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timer_ro : std_logic;
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end record;
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end record;
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| Line 145... |
Line 150... |
signal update_ctmr : std_logic_vector(3 downto 0);
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signal update_ctmr : std_logic_vector(3 downto 0);
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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Interrupt_PIT <= pit.timer_ro;
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Interrupt_PIT <= pit.timer_ro;
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Interrupt_RTC <= rtc.frac_ro;
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Interrupt_RTC <= rtc.frac_ro;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel_q <= "000";
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Wr_En_q <= '0';
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Wr_Data_q <= x"00";
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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pit.timer_cnt <= x"00";
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pit.timer_cnt <= x"00";
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pit.timer_ro <= '0';
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pit.timer_ro <= '0';
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rtc.frac <= DECISEC;
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rtc.frac <= DECISEC;
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rtc.frac_ro <= '0';
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rtc.frac_ro <= '0';
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| Line 197... |
Line 210... |
update_ctmr <= (others => '0');
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update_ctmr <= (others => '0');
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interval <= x"00";
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interval <= x"00";
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update_interval <= '0';
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update_interval <= '0';
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Wr_Data_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
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Wr_En <= '0';
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Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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-- Periodic Interval Timer
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-- Periodic Interval Timer
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pit.timer_cnt <= pit.timer_cnt - uSec_Tick;
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pit.timer_cnt <= pit.timer_cnt - uSec_Tick;
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pit.timer_ro <= '0';
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pit.timer_ro <= '0';
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| Line 327... |
Line 334... |
update_shd <= '0';
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update_shd <= '0';
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end if;
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end if;
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update_interval <= '0';
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update_interval <= '0';
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Reg_Addr_q <= Reg_Addr;
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Reg_Sel_q <= Reg_Sel_d;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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Wr_En_q <= Wr_En_d;
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Wr_Data_q <= Wr_Data_d;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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update_rtc <= '0';
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update_rtc <= '0';
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if( Wr_En = '1' )then
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if( Wr_En_q = '1' )then
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case( Reg_Addr_q )is
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case( Reg_Sel_q )is
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when "000" =>
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when "000" =>
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interval <= Wr_Data_q;
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interval <= Wr_Data_q;
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update_interval <= '1';
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update_interval <= '1';
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when "001" =>
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when "001" =>
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| Line 371... |
Line 379... |
update_ctmr <= update_ctmr - or_reduce(update_ctmr);
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update_ctmr <= update_ctmr - or_reduce(update_ctmr);
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if( rtc.frac_ro = '1' )then
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if( rtc.frac_ro = '1' )then
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update_ctmr <= (others => '1');
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update_ctmr <= (others => '1');
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end if;
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end if;
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Rd_En_q <= Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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if( Rd_En_q = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Addr_q )is
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when "000" =>
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when "000" =>
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Rd_Data <= interval;
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Rd_Data <= interval;
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when "001" =>
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when "001" =>
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Rd_Data <= shd_tens;
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Rd_Data <= shd_tens;
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when "010" =>
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when "010" =>
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