| Line 31... |
Line 31... |
-- "0_1111_1110" (0x0FE) Clock Status*
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-- "0_1111_1110" (0x0FE) Clock Status*
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-- "0_1111_1111" (0x0FF) TX Length / Status**
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-- "0_1111_1111" (0x0FF) TX Length / Status**
|
--
|
--
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-- Receive Memory Map
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-- Receive Memory Map
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-- "1_0000_0000" (0x100) RX Buffer START
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-- "1_0000_0000" (0x100) RX Buffer START
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-- "1_1111_1110" (0x1FE) RX Buffer END
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-- "1_1111_1101" (0x1FD) RX Buffer END
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-- "1_1111_1111" (0x1FF) RX Length / Status
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-- "1_1111_1110" (0x0FE) Reserved
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-- "1_1111_1111" (0x1FF) RX Length / Status***
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--
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-- * Address 0xFE reports the SDLC bit clock status and updates on changes.
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-- 1) If BClk_Okay = '0' (Bitclock is NOT present), the field will report
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-- 0x00. Otherwise, it will report 0xFF if the bitclock is present.
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-- 2) Writing any value to the register will cause the controller to
|
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-- silently reset the clock status without causing an interrupt.
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--
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--
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-- * Address 0xFE reports the SDLC bit clock status and updates on changes. If
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-- ** This location serves as the control/status register for transmit
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-- the bit clock goes away (BClk_Okay = '0'), the field will report 0x00.
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-- 1) Writing a value between 1 and 253 will trigger the transmit engine,
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-- otherwise it will report 0xFF. Note that the CPU can overwrite this
|
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-- location, at which point the status will be invalid.
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--
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-- ** This location serves as the control/status register for the interface
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-- 1) Writing 0x00 will reset the clock status flag in 0xFE without
|
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-- triggering an interrupt.
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-- 2) Writing a value between 1 and 253 will trigger the transmit engine,
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-- using the write value as the packet length.
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-- using the write value as the packet length.
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-- 3) Writing 0xFE or 0xFF will be ignored by the engine.
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-- 2) Values 0x00, 0xFE, or 0xFF are invalid, and will be ignored.
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-- 4) This value will change from the user written value to 0xFF once the
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-- 3) This value will change from the user written value to 0xFF once the
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-- packet is transmitted.
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-- packet is transmitted to indicate the transmission is complete.
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--
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--
|
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-- *** This location serves as the status register for the receive
|
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-- 1) This value is only updated on reception of a full frame, indicated
|
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-- by a start followed by a stop flag. Incomplete frames are ignored.
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-- 2) If the packet CRC matches the transmitted CRC, the packet is
|
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-- considered valid, and the received length (less CRC) is written.
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-- 3) If the packet CRC doesn't match, a value of ERR_CHECKSUM is written.
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-- 4) If too many bytes are received (buffer overflow), a value of
|
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-- ERR_LENGTH is written.
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|
|
library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 62... |
Line 70... |
library work;
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library work;
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use work.sdlc_serial_pkg.all;
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use work.sdlc_serial_pkg.all;
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|
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entity o8_sdlc_if is
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entity o8_sdlc_if is
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generic(
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generic(
|
|
Monitor_Enable : boolean := true;
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Attach_Monitor_to_CPU_Side : boolean := false;
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Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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Set_As_Master : boolean := true;
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Set_As_Master : boolean := true;
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Clock_Offset : integer := 6;
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Clock_Offset : integer := 6;
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BitClock_Freq : real := 500000.0;
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BitClock_Freq : real := 500000.0;
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Sys_Freq : real := 100000000.0;
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Sys_Freq : real := 100000000.0;
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| Line 102... |
Line 112... |
signal RAM_Addr_Match : std_logic := '0';
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signal RAM_Addr_Match : std_logic := '0';
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signal RAM_Wr_En : std_logic := '0';
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signal RAM_Wr_En : std_logic := '0';
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signal RAM_Rd_En : std_logic := '0';
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signal RAM_Rd_En : std_logic := '0';
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signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
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signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
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|
|
constant Reg_Sub_Addr : std_logic_vector(8 downto 0) :=
|
constant Reg_Sub_Addr : std_logic_vector(8 downto 1) := x"7F";
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conv_std_logic_vector(255,9);
|
|
|
alias Reg_Upper_Addr is Bus_Address(8 downto 1);
|
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alias Reg_Lower_Addr is Bus_Address(0);
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|
|
signal Reg_Addr : std_logic_vector(8 downto 0) := (others => '0');
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signal Reg_Addr : std_logic_vector(8 downto 1) := (others => '0');
|
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signal Reg_Sel : std_logic := '0';
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signal Reg_Wr_En : std_logic := '0';
|
signal Reg_Wr_En : std_logic := '0';
|
signal Reg_Updated : std_logic := '0';
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signal Reg_Clk_Sel : std_logic := '0';
|
|
signal Reg_TxS_Sel : std_logic := '0';
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|
|
-- Connect the serial engine to the dual-port memory
|
-- Connect the serial engine to the dual-port memory
|
signal DP_Addr : std_logic_vector(8 downto 0) := (others => '0');
|
signal DP_Addr : std_logic_vector(8 downto 0) := (others => '0');
|
signal DP_Wr_Data : DATA_IN_TYPE := x"00";
|
signal DP_Wr_Data : DATA_IN_TYPE := x"00";
|
signal DP_Wr_En : std_logic := '0';
|
signal DP_Wr_En : std_logic := '0';
|
signal DP_Rd_Data : DATA_IN_TYPE := x"00";
|
signal DP_Rd_Data : DATA_IN_TYPE := x"00";
|
| Line 153... |
Line 168... |
CPU_RAM_proc: process( Reset, Clock )
|
CPU_RAM_proc: process( Reset, Clock )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Reg_Addr <= (others => '0');
|
Reg_Addr <= (others => '0');
|
Reg_Wr_En <= '0';
|
Reg_Wr_En <= '0';
|
Reg_Updated <= '0';
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Reg_Clk_Sel <= '0';
|
|
Reg_TxS_Sel <= '0';
|
RAM_Rd_En <= '0';
|
RAM_Rd_En <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
Reg_Addr <= RAM_Lower_Addr;
|
Reg_Addr <= Reg_Upper_Addr;
|
|
Reg_Sel <= Reg_Lower_Addr;
|
Reg_Wr_En <= RAM_Addr_Match and Wr_Enable;
|
Reg_Wr_En <= RAM_Addr_Match and Wr_Enable;
|
|
|
Reg_Updated <= '0';
|
Reg_Clk_Sel <= '0';
|
|
Reg_TxS_Sel <= '0';
|
if( Reg_Addr = Reg_Sub_Addr )then
|
if( Reg_Addr = Reg_Sub_Addr )then
|
Reg_Updated <= Reg_Wr_En;
|
Reg_Clk_Sel <= Reg_Wr_En and not Reg_Sel;
|
|
Reg_TxS_Sel <= Reg_Wr_En and Reg_Sel;
|
end if;
|
end if;
|
|
|
RAM_Rd_En <= RAM_Addr_Match and Rd_Enable;
|
RAM_Rd_En <= RAM_Addr_Match and Rd_Enable;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
if( RAM_Rd_En = '1' )then
|
if( RAM_Rd_En = '1' )then
|
| Line 186... |
Line 205... |
wren_b => DP_Wr_En,
|
wren_b => DP_Wr_En,
|
q_a => Rd_Data_i,
|
q_a => Rd_Data_i,
|
q_b => DP_Rd_Data
|
q_b => DP_Rd_Data
|
);
|
);
|
|
|
|
Attach_to_CPU_side: if( Monitor_Enable and Attach_Monitor_to_CPU_Side )generate
|
|
|
|
U_MON: entity work.monitor
|
|
port map(
|
|
clock => Clock,
|
|
address => RAM_Lower_Addr,
|
|
data => Wr_Data,
|
|
wren => RAM_Wr_En,
|
|
q => open
|
|
);
|
|
end generate;
|
|
|
|
Attach_to_Int_side: if( Monitor_Enable and not Attach_Monitor_to_CPU_Side )generate
|
|
|
|
U_MON: entity work.monitor
|
|
port map(
|
|
clock => Clock,
|
|
address => DP_Addr,
|
|
data => DP_Wr_Data,
|
|
wren => DP_Wr_En,
|
|
q => open
|
|
);
|
|
|
|
end generate;
|
|
|
U_BCLK : entity work.sdlc_serial_clk
|
U_BCLK : entity work.sdlc_serial_clk
|
generic map(
|
generic map(
|
Set_As_Master => Set_As_Master,
|
Set_As_Master => Set_As_Master,
|
BitClock_Freq => BitClock_Freq,
|
BitClock_Freq => BitClock_Freq,
|
Reset_Level => Reset_Level,
|
Reset_Level => Reset_Level,
|
| Line 214... |
Line 258... |
Clock => Clock,
|
Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
--
|
--
|
BClk_Okay => BClk_Okay,
|
BClk_Okay => BClk_Okay,
|
--
|
--
|
Reg_Updated => Reg_Updated,
|
Reg_Clk_Sel => Reg_Clk_Sel,
|
|
Reg_TxS_Sel => Reg_TxS_Sel,
|
--
|
--
|
DP_Addr => DP_Addr,
|
DP_Addr => DP_Addr,
|
DP_Wr_Data => DP_Wr_Data,
|
DP_Wr_Data => DP_Wr_Data,
|
DP_Wr_En => DP_Wr_En,
|
DP_Wr_En => DP_Wr_En,
|
DP_Rd_Data => DP_Rd_Data,
|
DP_Rd_Data => DP_Rd_Data,
|
