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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sdlc_if.vhd] - Diff between revs 198 and 199
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| Rev 198 |
Rev 199 |
| Line 70... |
Line 70... |
library work;
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library work;
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use work.sdlc_serial_pkg.all;
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use work.sdlc_serial_pkg.all;
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entity o8_sdlc_if is
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entity o8_sdlc_if is
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generic(
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generic(
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Monitor_Enable : boolean := true;
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Attach_Monitor_to_CPU_Side : boolean := false;
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Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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Set_As_Master : boolean := true;
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Set_As_Master : boolean := true;
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Clock_Offset : integer := 6;
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Clock_Offset : integer := 6;
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BitClock_Freq : real := 500000.0;
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BitClock_Freq : real := 500000.0;
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Sys_Freq : real := 100000000.0;
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Sys_Freq : real := 100000000.0;
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| Line 203... |
Line 205... |
wren_b => DP_Wr_En,
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wren_b => DP_Wr_En,
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q_a => Rd_Data_i,
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q_a => Rd_Data_i,
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q_b => DP_Rd_Data
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q_b => DP_Rd_Data
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);
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);
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Attach_to_CPU_side: if( Monitor_Enable and Attach_Monitor_to_CPU_Side )generate
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U_MON: entity work.sdlc_monitor
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port map(
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clock => Clock,
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address => RAM_Lower_Addr,
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data => Wr_Data,
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wren => RAM_Wr_En,
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q => open
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);
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end generate;
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Attach_to_Int_side: if( Monitor_Enable and not Attach_Monitor_to_CPU_Side )generate
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U_MON: entity work.sdlc_monitor
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port map(
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clock => Clock,
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address => DP_Addr,
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data => DP_Wr_Data,
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wren => DP_Wr_En,
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q => open
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);
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end generate;
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U_BCLK : entity work.sdlc_serial_clk
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U_BCLK : entity work.sdlc_serial_clk
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generic map(
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generic map(
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Set_As_Master => Set_As_Master,
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Set_As_Master => Set_As_Master,
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BitClock_Freq => BitClock_Freq,
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BitClock_Freq => BitClock_Freq,
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Reset_Level => Reset_Level,
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Reset_Level => Reset_Level,
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