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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sdlc_if.vhd] - Diff between revs 200 and 201

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Rev 200 Rev 201
Line 32... Line 32...
-- "0_1111_1111" (0x0FF) TX Length / Status**
-- "0_1111_1111" (0x0FF) TX Length / Status**
--
--
-- Receive Memory Map
-- Receive Memory Map
-- "1_0000_0000" (0x100) RX Buffer START
-- "1_0000_0000" (0x100) RX Buffer START
-- "1_1111_1101" (0x1FD) RX Buffer END
-- "1_1111_1101" (0x1FD) RX Buffer END
-- "1_1111_1110" (0x0FE) Reserved
-- "1_1111_1110" (0x0FE) RX Checksum Status***
-- "1_1111_1111" (0x1FF) RX Length / Status***
-- "1_1111_1111" (0x1FF) RX Length   Status****
--
--
-- *   Address 0xFE reports the SDLC bit clock status and updates on changes.
-- *   Address 0xFE reports the SDLC bit clock status and updates on changes.
--     1) If BClk_Okay = '0' (Bitclock is NOT present), the field will report
--     1) If BClk_Okay = '0' (Bitclock is NOT present), the field will report
--         0x00. Otherwise, it will report 0xFF if the bitclock is present.
--         0x00. Otherwise, it will report 0xFF if the bitclock is present.
--     2) Writing any value to the register will cause the controller to
--     2) Writing any value to the register will cause the controller to
Line 48... Line 48...
--         using the write value as the packet length.
--         using the write value as the packet length.
--     2) Values 0x00, 0xFE, or 0xFF are invalid, and will be ignored.
--     2) Values 0x00, 0xFE, or 0xFF are invalid, and will be ignored.
--     3) This value will change from the user written value to 0xFF once the
--     3) This value will change from the user written value to 0xFF once the
--         packet is transmitted to indicate the transmission is complete.
--         packet is transmitted to indicate the transmission is complete.
--
--
-- *** This location serves as the status register for the receive
-- ***  This location serves as the status register for receive checksum test
 
--      1) A value of 0x00 indicates the CRC did NOT match, while a value
 
--         of 0xFF indicates that the recieved CRC matches the calculated CRC.
 
--
 
-- **** This location serves as the status register for the receive
--     1) This value is only updated on reception of a full frame, indicated
--     1) This value is only updated on reception of a full frame, indicated
--         by a start followed by a stop flag. Incomplete frames are ignored.
--         by a start followed by a stop flag. Incomplete frames are ignored.
--     2) If the packet CRC matches the transmitted CRC, the packet is
--     2) If the packet CRC matches the transmitted CRC, the packet is
--         considered valid, and the received length (less CRC) is written.
--         considered valid, and the received length (less CRC) is written.
--     3) If the packet CRC doesn't match, a value of ERR_CHECKSUM is written.
--     3) If the packet CRC doesn't match, a value of ERR_CHECKSUM is written.

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