| Line 74... |
Line 74... |
library work;
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library work;
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use work.sdlc_serial_pkg.all;
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use work.sdlc_serial_pkg.all;
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entity o8_sdlc_if is
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entity o8_sdlc_if is
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generic(
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generic(
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Monitor_Enable : boolean := true;
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Monitor_Enable : boolean := false;
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Attach_Monitor_to_CPU_Side : boolean := false;
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Attach_Monitor_to_CPU_Side : boolean := false;
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Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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Set_As_Master : boolean := true;
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Set_As_Master : boolean := true;
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Clock_Offset : integer := 6;
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Clock_Offset : integer := 6;
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BitClock_Freq : real := 500000.0;
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BitClock_Freq : real := 500000.0;
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| Line 127... |
Line 127... |
signal Reg_Sel : std_logic := '0';
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signal Reg_Sel : std_logic := '0';
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signal Reg_Wr_En : std_logic := '0';
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signal Reg_Wr_En : std_logic := '0';
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signal Reg_Clk_Sel : std_logic := '0';
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signal Reg_Clk_Sel : std_logic := '0';
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signal Reg_TxS_Sel : std_logic := '0';
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signal Reg_TxS_Sel : std_logic := '0';
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-- Connect the serial engine to the dual-port memory
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signal DP_Addr : std_logic_vector(8 downto 0) := (others => '0');
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signal DP_Addr : std_logic_vector(8 downto 0) := (others => '0');
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signal DP_Wr_Data : DATA_IN_TYPE := x"00";
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signal DP_Wr_Data : DATA_IN_TYPE := x"00";
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signal DP_Wr_En : std_logic := '0';
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signal DP_Wr_En : std_logic := '0';
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signal DP_Rd_Data : DATA_IN_TYPE := x"00";
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signal DP_Rd_Data : DATA_IN_TYPE := x"00";
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signal DP_Port0_Addr : DATA_IN_TYPE := x"00";
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signal DP_Port0_RWn : std_logic := '0';
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signal DP_Port0_WrData : DATA_IN_TYPE := x"00";
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signal DP_Port0_RdData : DATA_IN_TYPE := x"00";
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signal DP_Port0_Req : std_logic := '0';
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signal DP_Port0_Ack : std_logic := '0';
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signal DP_Port1_Addr : DATA_IN_TYPE := x"00";
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signal DP_Port1_RWn : std_logic := '0';
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signal DP_Port1_WrData : DATA_IN_TYPE := x"00";
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signal DP_Port1_RdData : DATA_IN_TYPE := x"00";
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signal DP_Port1_Req : std_logic := '0';
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signal DP_Port1_Ack : std_logic := '0';
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signal BClk_RE : std_logic := '0';
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signal BClk_RE : std_logic := '0';
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signal BClk_FE : std_logic := '0';
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signal BClk_FE : std_logic := '0';
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signal BClk_Okay : std_logic := '0';
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signal TX_Wr_En : std_logic := '0';
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signal TX_Wr_En : std_logic := '0';
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signal TX_Wr_Flag : std_logic := '0';
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signal TX_Wr_Flag : std_logic := '0';
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signal TX_Wr_Data : DATA_IN_TYPE := x"00";
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signal TX_Wr_Data : DATA_IN_TYPE := x"00";
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signal TX_Req_Next : std_logic := '0';
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signal TX_Req_Next : std_logic := '0';
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signal TX_CRC_Clr : std_logic := '0';
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signal TX_CRC_Clr : std_logic := '0';
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signal TX_CRC_En : std_logic := '0';
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signal TX_CRC_En : std_logic := '0';
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signal TX_CRC_Data : CRC_OUT_TYPE := x"0000";
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signal TX_CRC_Data : CRC_OUT_TYPE := x"0000";
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alias TX_CRC_Data_LB is TX_CRC_Data(7 downto 0);
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alias TX_CRC_Data_UB is TX_CRC_Data(15 downto 8);
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signal TX_CRC_Valid : std_logic := '0';
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signal TX_CRC_Valid : std_logic := '0';
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signal TX_Interrupt : std_logic := '0';
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signal RX_Valid : std_logic := '0';
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signal RX_Valid : std_logic := '0';
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signal RX_Flag : std_logic := '0';
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signal RX_Flag : std_logic := '0';
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signal RX_Data : DATA_IN_TYPE := x"00";
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signal RX_Data : DATA_IN_TYPE;
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signal RX_Idle : std_logic := '0';
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signal RX_Idle : std_logic := '0';
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signal RX_CRC_Clr : std_logic := '0';
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signal RX_Frame_Start : std_logic := '0';
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signal RX_CRC_En : std_logic := '0';
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signal RX_Frame_Stop : std_logic := '0';
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signal RX_CRC_Data : CRC_OUT_TYPE := x"0000";
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signal RX_Frame_Valid : std_logic := '0';
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signal RX_Frame_Data : DATA_IN_TYPE := x"00";
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signal RX_CRC_Valid : std_logic := '0';
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signal RX_CRC_Valid : std_logic := '0';
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signal RX_CRC_Data : CRC_OUT_TYPE := x"0000";
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signal BClk_Okay : std_logic := '0';
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signal RX_Interrupt : std_logic := '0';
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begin
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begin
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-- ***************************************************************************
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-- * Open8 Bus Interface and Control Register Detection *
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-- ***************************************************************************
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-- This decode needs to happen immediately, to give the RAM a chance to
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-- This decode needs to happen immediately, to give the RAM a chance to
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-- do the lookup before we have to set Rd_Data
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-- do the lookup before we have to set Rd_Data
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RAM_Addr_Match <= '1' when Base_Addr = RAM_Upper_Addr else '0';
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RAM_Addr_Match <= '1' when Base_Addr = RAM_Upper_Addr else '0';
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RAM_Wr_En <= RAM_Addr_Match and Wr_Enable;
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RAM_Wr_En <= RAM_Addr_Match and Wr_Enable;
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| Line 196... |
Line 217... |
Rd_Data <= Rd_Data_i;
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Rd_Data <= Rd_Data_i;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- ***************************************************************************
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-- * Shared Dual-Port Memory *
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-- ***************************************************************************
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U_RAM : entity work.sdlc_dp512b_ram
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U_RAM : entity work.sdlc_dp512b_ram
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port map(
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port map(
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clock => Clock,
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clock => Clock,
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address_a => RAM_Lower_Addr,
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address_a => RAM_Lower_Addr,
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address_b => DP_Addr,
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address_b => DP_Addr,
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| Line 234... |
Line 259... |
q => open
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q => open
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);
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);
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end generate;
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end generate;
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-- ***************************************************************************
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-- * Memory Arbitration *
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-- ***************************************************************************
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U_ARB : entity work.sdlc_serial_arbfsm
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generic map(
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Reset_Level => Reset_Level
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)
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port map(
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Clock => Clock,
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Reset => Reset,
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--
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DP_Port0_Addr => DP_Port0_Addr,
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DP_Port0_RWn => DP_Port0_RWn,
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DP_Port0_WrData => DP_Port0_WrData,
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DP_Port0_RdData => DP_Port0_RdData,
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DP_Port0_Req => DP_Port0_Req,
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DP_Port0_Ack => DP_Port0_Ack,
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--
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DP_Port1_Addr => DP_Port1_Addr,
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DP_Port1_RWn => DP_Port1_RWn,
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DP_Port1_WrData => DP_Port1_WrData,
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DP_Port1_RdData => DP_Port1_RdData,
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DP_Port1_Req => DP_Port1_Req,
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DP_Port1_Ack => DP_Port1_Ack,
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--
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DP_Addr => DP_Addr,
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DP_Wr_Data => DP_Wr_Data,
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DP_Wr_En => DP_Wr_En,
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DP_Rd_Data => DP_Rd_Data
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);
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-- ***************************************************************************
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-- * Serial BitClock *
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-- ***************************************************************************
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U_BCLK : entity work.sdlc_serial_clk
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U_BCLK : entity work.sdlc_serial_clk
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generic map(
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generic map(
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Set_As_Master => Set_As_Master,
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Set_As_Master => Set_As_Master,
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BitClock_Freq => BitClock_Freq,
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BitClock_Freq => BitClock_Freq,
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Reset_Level => Reset_Level,
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Reset_Level => Reset_Level,
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| Line 252... |
Line 313... |
BClk_FE => BClk_FE,
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BClk_FE => BClk_FE,
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BClk_RE => BClk_RE,
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BClk_RE => BClk_RE,
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BClk_Okay => BClk_Okay
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BClk_Okay => BClk_Okay
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);
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);
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U_CTRL : entity work.sdlc_serial_ctrl
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-- ***************************************************************************
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-- * Serial Transmit Path *
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-- ***************************************************************************
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U_TXFSM: entity work.sdlc_serial_txfsm
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generic map(
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generic map(
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Reset_Level => Reset_Level
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Reset_Level => Reset_Level
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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| Line 265... |
Line 330... |
BClk_Okay => BClk_Okay,
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BClk_Okay => BClk_Okay,
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--
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--
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Reg_Clk_Sel => Reg_Clk_Sel,
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Reg_Clk_Sel => Reg_Clk_Sel,
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Reg_TxS_Sel => Reg_TxS_Sel,
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Reg_TxS_Sel => Reg_TxS_Sel,
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--
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--
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DP_Addr => DP_Addr,
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DP_Port0_Addr => DP_Port0_Addr,
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DP_Wr_Data => DP_Wr_Data,
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DP_Port0_RWn => DP_Port0_RWn,
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DP_Wr_En => DP_Wr_En,
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DP_Port0_WrData => DP_Port0_WrData,
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DP_Rd_Data => DP_Rd_Data,
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DP_Port0_RdData => DP_Port0_RdData,
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DP_Port0_Req => DP_Port0_Req,
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DP_Port0_Ack => DP_Port0_Ack,
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--
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--
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TX_Wr_En => TX_Wr_En,
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TX_Wr_En => TX_Wr_En,
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TX_Wr_Flag => TX_Wr_Flag,
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TX_Wr_Flag => TX_Wr_Flag,
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TX_Wr_Data => TX_Wr_Data,
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TX_Wr_Data => TX_Wr_Data,
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TX_Req_Next => TX_Req_Next,
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TX_Req_Next => TX_Req_Next,
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| Line 280... |
Line 347... |
TX_CRC_Clr => TX_CRC_Clr,
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TX_CRC_Clr => TX_CRC_Clr,
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TX_CRC_En => TX_CRC_En,
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TX_CRC_En => TX_CRC_En,
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TX_CRC_Data => TX_CRC_Data,
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TX_CRC_Data => TX_CRC_Data,
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TX_CRC_Valid => TX_CRC_Valid,
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TX_CRC_Valid => TX_CRC_Valid,
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--
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--
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RX_Valid => RX_Valid,
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TX_Interrupt => TX_Interrupt
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RX_Flag => RX_Flag,
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);
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RX_Data => RX_Data,
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RX_Idle => RX_Idle,
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U_TX_CRC : entity work.sdlc_crc16_ccitt
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generic map(
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Poly_Init => Poly_Init,
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Reset_Level => Reset_Level
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)
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port map(
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Clock => Clock,
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Reset => Reset,
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--
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--
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RX_CRC_Clr => RX_CRC_Clr,
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Clear => TX_CRC_Clr,
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RX_CRC_En => RX_CRC_En,
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Wr_En => TX_CRC_En,
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RX_CRC_Data => RX_CRC_Data,
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Wr_Data => TX_Wr_Data,
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RX_CRC_Valid => RX_CRC_Valid,
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--
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--
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Interrupt => Interrupt
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CRC16_Valid => TX_CRC_Valid,
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CRC16_Out => TX_CRC_Data
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);
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);
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U_TX_SER : entity work.sdlc_serial_tx
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U_TX_SER : entity work.sdlc_serial_tx
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generic map(
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generic map(
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Reset_Level => Reset_Level
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Reset_Level => Reset_Level
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| Line 313... |
Line 387... |
TX_Req_Next => TX_Req_Next,
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TX_Req_Next => TX_Req_Next,
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--
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--
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Serial_Out => SDLC_Out
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Serial_Out => SDLC_Out
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);
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);
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U_TX_CRC : entity work.sdlc_crc16_ccitt
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-- ***************************************************************************
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generic map(
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-- * Serial Receive Path *
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Poly_Init => Poly_Init,
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-- ***************************************************************************
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Reset_Level => Reset_Level
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)
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port map(
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Clock => Clock,
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Reset => Reset,
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--
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Clear => TX_CRC_Clr,
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Wr_Data => TX_Wr_Data,
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Wr_En => TX_CRC_En,
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--
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CRC16_Out => TX_CRC_Data,
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CRC16_Valid => TX_CRC_Valid
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);
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U_RX_SER : entity work.sdlc_serial_rx
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U_RX_SER : entity work.sdlc_serial_rx
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generic map(
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generic map(
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Set_As_Master => Set_As_Master,
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Set_As_Master => Set_As_Master,
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Clock_Offset => Clock_Offset,
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Clock_Offset => Clock_Offset,
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| Line 351... |
Line 412... |
RX_Flag => RX_Flag,
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RX_Flag => RX_Flag,
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RX_Data => RX_Data,
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RX_Data => RX_Data,
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RX_Idle => RX_Idle
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RX_Idle => RX_Idle
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);
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);
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U_RX_PKT : entity work.sdlc_serial_frame
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generic map(
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Reset_Level => Reset_Level
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)
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port map(
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Clock => Clock,
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Reset => Reset,
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--
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RX_Valid => RX_Valid,
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RX_Flag => RX_Flag,
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RX_Data => RX_Data,
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RX_Idle => RX_Idle,
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--
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RX_Frame_Start => RX_Frame_Start,
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RX_Frame_Stop => RX_Frame_Stop,
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RX_Frame_Valid => RX_Frame_Valid,
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RX_Frame_Data => RX_Frame_Data
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);
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U_RX_CRC : entity work.sdlc_crc16_ccitt
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U_RX_CRC : entity work.sdlc_crc16_ccitt
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generic map(
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generic map(
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Poly_Init => Poly_Init,
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Poly_Init => Poly_Init,
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Reset_Level => Reset_Level
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Reset_Level => Reset_Level
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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--
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--
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Clear => RX_CRC_Clr,
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Clear => RX_Frame_Start,
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Wr_Data => RX_Data,
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Wr_En => RX_Frame_Valid,
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Wr_En => RX_CRC_En,
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Wr_Data => RX_Frame_Data,
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--
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CRC16_Valid => RX_CRC_Valid,
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CRC16_Out => RX_CRC_Data
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);
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U_RX_FSM : entity work.sdlc_serial_rxfsm
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generic map(
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Reset_Level => Reset_Level
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)
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port map(
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Clock => Clock,
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Reset => Reset,
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--
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BClk_Okay => BClk_Okay,
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--
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DP_Port1_Addr => DP_Port1_Addr,
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DP_Port1_RWn => DP_Port1_RWn,
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DP_Port1_WrData => DP_Port1_WrData,
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DP_Port1_RdData => DP_Port1_RdData,
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DP_Port1_Req => DP_Port1_Req,
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DP_Port1_Ack => DP_Port1_Ack,
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--
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RX_CRC_Valid => RX_CRC_Valid,
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RX_CRC_Data => RX_CRC_Data,
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--
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RX_Frame_Start => RX_Frame_Start,
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RX_Frame_Stop => RX_Frame_Stop,
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RX_Frame_Valid => RX_Frame_Valid,
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RX_Frame_Data => RX_Frame_Data,
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--
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--
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CRC16_Out => RX_CRC_Data,
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RX_Interrupt => RX_Interrupt
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CRC16_Valid => RX_CRC_Valid
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);
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);
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-- ***************************************************************************
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-- * Merge Interrupts *
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-- ***************************************************************************
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Interrupt_merge_proc: process( Clock, Reset )
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begin
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if( Reset = Reset_Level )then
|
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Interrupt <= '0';
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elsif( rising_edge(Clock) )then
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Interrupt <= RX_Interrupt or TX_Interrupt;
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end if;
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end process;
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end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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