| Line 101... |
Line 101... |
);
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);
|
end entity;
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end entity;
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|
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architecture behave of o8_sdlc_if is
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architecture behave of o8_sdlc_if is
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|
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-- Connect the CPU to the dual-port memory
|
|
constant Base_Addr : std_logic_vector(15 downto 9)
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constant Base_Addr : std_logic_vector(15 downto 9)
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:= Address(15 downto 9);
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:= Address(15 downto 9);
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|
|
alias RAM_Upper_Addr is Bus_Address(15 downto 9);
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alias CPU_Upper_Addr is Bus_Address(15 downto 9);
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alias RAM_Lower_Addr is Bus_Address(8 downto 0);
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signal Base_Addr_Match : std_logic := '0';
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|
|
signal RAM_Addr_Match : std_logic := '0';
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alias DP_A_Addr is Bus_Address(8 downto 0);
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signal RAM_Wr_En : std_logic := '0';
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signal DP_A_Wr_En : std_logic := '0';
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signal RAM_Rd_En : std_logic := '0';
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alias DP_A_Wr_Data is Wr_Data;
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signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
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signal DP_A_Rd_En : std_logic := '0';
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signal DP_A_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
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|
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constant Reg_Sub_Addr : std_logic_vector(8 downto 1) := x"7F";
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constant Reg_Sub_Addr : std_logic_vector(8 downto 1) := x"7F";
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|
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alias Reg_Upper_Addr is Bus_Address(8 downto 1);
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alias Reg_Upper_Addr is Bus_Address(8 downto 1);
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alias Reg_Lower_Addr is Bus_Address(0);
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alias Reg_Lower_Addr is Bus_Address(0);
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|
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signal Reg_Addr : std_logic_vector(8 downto 1) := (others => '0');
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signal Reg_Addr : std_logic_vector(8 downto 1) := (others => '0');
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signal Reg_Sel : std_logic := '0';
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signal Reg_Sel : std_logic := '0';
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signal Reg_Wr_En : std_logic := '0';
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signal Reg_Wr_En : std_logic := '0';
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signal Reg_Clk_Sel : std_logic := '0';
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signal Reg_Clk_Sel : std_logic := '0';
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signal Reg_TxS_Sel : std_logic := '0';
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signal Reg_TxS_Sel : std_logic := '0';
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|
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signal DP_Addr : std_logic_vector(8 downto 0) := (others => '0');
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signal DP_B_Addr : std_logic_vector(8 downto 0) := (others => '0');
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signal DP_Wr_Data : DATA_IN_TYPE := x"00";
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signal DP_B_Wr_Data : DATA_IN_TYPE := x"00";
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signal DP_Wr_En : std_logic := '0';
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signal DP_B_Wr_En : std_logic := '0';
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signal DP_Rd_Data : DATA_IN_TYPE := x"00";
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signal DP_B_Rd_Data : DATA_IN_TYPE := x"00";
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|
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signal DP_Port0_Addr : DATA_IN_TYPE := x"00";
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signal DP_Port0_Addr : DATA_IN_TYPE := x"00";
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signal DP_Port0_RWn : std_logic := '0';
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signal DP_Port0_RWn : std_logic := '0';
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signal DP_Port0_WrData : DATA_IN_TYPE := x"00";
|
signal DP_Port0_WrData : DATA_IN_TYPE := x"00";
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signal DP_Port0_RdData : DATA_IN_TYPE := x"00";
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signal DP_Port0_RdData : DATA_IN_TYPE := x"00";
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| Line 182... |
Line 181... |
-- * Open8 Bus Interface and Control Register Detection *
|
-- * Open8 Bus Interface and Control Register Detection *
|
-- ***************************************************************************
|
-- ***************************************************************************
|
|
|
-- This decode needs to happen immediately, to give the RAM a chance to
|
-- This decode needs to happen immediately, to give the RAM a chance to
|
-- do the lookup before we have to set Rd_Data
|
-- do the lookup before we have to set Rd_Data
|
RAM_Addr_Match <= '1' when Base_Addr = RAM_Upper_Addr else '0';
|
Base_Addr_Match <= '1' when Base_Addr = CPU_Upper_Addr else '0';
|
RAM_Wr_En <= RAM_Addr_Match and Wr_Enable;
|
DP_A_Wr_En <= Base_Addr_Match and Wr_Enable;
|
|
|
CPU_RAM_proc: process( Reset, Clock )
|
CPU_RAM_proc: process( Reset, Clock )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Reg_Addr <= (others => '0');
|
Reg_Addr <= (others => '0');
|
Reg_Wr_En <= '0';
|
Reg_Wr_En <= '0';
|
Reg_Clk_Sel <= '0';
|
Reg_Clk_Sel <= '0';
|
Reg_TxS_Sel <= '0';
|
Reg_TxS_Sel <= '0';
|
RAM_Rd_En <= '0';
|
DP_A_Rd_En <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
Reg_Addr <= Reg_Upper_Addr;
|
Reg_Addr <= Reg_Upper_Addr;
|
Reg_Sel <= Reg_Lower_Addr;
|
Reg_Sel <= Reg_Lower_Addr;
|
Reg_Wr_En <= RAM_Addr_Match and Wr_Enable;
|
Reg_Wr_En <= Base_Addr_Match and Wr_Enable;
|
|
|
Reg_Clk_Sel <= '0';
|
Reg_Clk_Sel <= '0';
|
Reg_TxS_Sel <= '0';
|
Reg_TxS_Sel <= '0';
|
if( Reg_Addr = Reg_Sub_Addr )then
|
if( Reg_Addr = Reg_Sub_Addr )then
|
Reg_Clk_Sel <= Reg_Wr_En and not Reg_Sel;
|
Reg_Clk_Sel <= Reg_Wr_En and not Reg_Sel;
|
Reg_TxS_Sel <= Reg_Wr_En and Reg_Sel;
|
Reg_TxS_Sel <= Reg_Wr_En and Reg_Sel;
|
end if;
|
end if;
|
|
|
RAM_Rd_En <= RAM_Addr_Match and Rd_Enable;
|
DP_A_Rd_En <= Base_Addr_Match and Rd_Enable;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
if( RAM_Rd_En = '1' )then
|
if( DP_A_Rd_En = '1' )then
|
Rd_Data <= Rd_Data_i;
|
Rd_Data <= DP_A_Rd_Data;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- ***************************************************************************
|
-- ***************************************************************************
|
| Line 221... |
Line 220... |
-- ***************************************************************************
|
-- ***************************************************************************
|
|
|
U_RAM : entity work.sdlc_dp512b_ram
|
U_RAM : entity work.sdlc_dp512b_ram
|
port map(
|
port map(
|
clock => Clock,
|
clock => Clock,
|
address_a => RAM_Lower_Addr,
|
address_a => DP_A_Addr,
|
address_b => DP_Addr,
|
address_b => DP_B_Addr,
|
data_a => Wr_Data,
|
data_a => DP_A_Wr_Data,
|
data_b => DP_Wr_Data,
|
data_b => DP_B_Wr_Data,
|
wren_a => RAM_Wr_En,
|
wren_a => DP_A_Wr_En,
|
wren_b => DP_Wr_En,
|
wren_b => DP_B_Wr_En,
|
q_a => Rd_Data_i,
|
q_a => DP_A_Rd_Data,
|
q_b => DP_Rd_Data
|
q_b => DP_B_Rd_Data
|
);
|
);
|
|
|
Attach_to_CPU_side: if( Monitor_Enable and Attach_Monitor_to_CPU_Side )generate
|
Attach_to_CPU_side: if( Monitor_Enable and Attach_Monitor_to_CPU_Side )generate
|
|
|
U_MON: entity work.sdlc_monitor
|
U_MON: entity work.sdlc_monitor
|
port map(
|
port map(
|
clock => Clock,
|
clock => Clock,
|
address => RAM_Lower_Addr,
|
address => DP_A_Addr,
|
data => Wr_Data,
|
data => DP_A_Wr_Data,
|
wren => RAM_Wr_En,
|
wren => DP_A_Wr_En,
|
q => open
|
q => open
|
);
|
);
|
end generate;
|
end generate;
|
|
|
Attach_to_Int_side: if( Monitor_Enable and not Attach_Monitor_to_CPU_Side )generate
|
Attach_to_Int_side: if( Monitor_Enable and not Attach_Monitor_to_CPU_Side )generate
|
|
|
U_MON: entity work.sdlc_monitor
|
U_MON: entity work.sdlc_monitor
|
port map(
|
port map(
|
clock => Clock,
|
clock => Clock,
|
address => DP_Addr,
|
address => DP_B_Addr,
|
data => DP_Wr_Data,
|
data => DP_B_Wr_Data,
|
wren => DP_Wr_En,
|
wren => DP_B_Wr_En,
|
q => open
|
q => open
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
| Line 268... |
Line 267... |
)
|
)
|
port map(
|
port map(
|
Clock => Clock,
|
Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
--
|
--
|
|
DP_Addr => DP_B_Addr,
|
|
DP_Wr_Data => DP_B_Wr_Data,
|
|
DP_Wr_En => DP_B_Wr_En,
|
|
DP_Rd_Data => DP_B_Rd_Data,
|
|
--
|
DP_Port0_Addr => DP_Port0_Addr,
|
DP_Port0_Addr => DP_Port0_Addr,
|
DP_Port0_RWn => DP_Port0_RWn,
|
DP_Port0_RWn => DP_Port0_RWn,
|
DP_Port0_WrData => DP_Port0_WrData,
|
DP_Port0_WrData => DP_Port0_WrData,
|
DP_Port0_RdData => DP_Port0_RdData,
|
DP_Port0_RdData => DP_Port0_RdData,
|
DP_Port0_Req => DP_Port0_Req,
|
DP_Port0_Req => DP_Port0_Req,
|
| Line 280... |
Line 284... |
DP_Port1_Addr => DP_Port1_Addr,
|
DP_Port1_Addr => DP_Port1_Addr,
|
DP_Port1_RWn => DP_Port1_RWn,
|
DP_Port1_RWn => DP_Port1_RWn,
|
DP_Port1_WrData => DP_Port1_WrData,
|
DP_Port1_WrData => DP_Port1_WrData,
|
DP_Port1_RdData => DP_Port1_RdData,
|
DP_Port1_RdData => DP_Port1_RdData,
|
DP_Port1_Req => DP_Port1_Req,
|
DP_Port1_Req => DP_Port1_Req,
|
DP_Port1_Ack => DP_Port1_Ack,
|
DP_Port1_Ack => DP_Port1_Ack
|
--
|
|
DP_Addr => DP_Addr,
|
|
DP_Wr_Data => DP_Wr_Data,
|
|
DP_Wr_En => DP_Wr_En,
|
|
DP_Rd_Data => DP_Rd_Data
|
|
);
|
);
|
|
|
-- ***************************************************************************
|
-- ***************************************************************************
|
-- * Serial BitClock *
|
-- * Serial BitClock *
|
-- ***************************************************************************
|
-- ***************************************************************************
|
