| Line 85... |
Line 85... |
);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Bus_Address : in ADDRESS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Wr_Enable : in std_logic;
|
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Wr_Data : in DATA_TYPE;
|
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Rd_Enable : in std_logic;
|
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic;
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Interrupt : out std_logic;
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-- Serial IO
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-- Serial IO
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SDLC_In : in std_logic;
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SDLC_In : in std_logic;
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SDLC_SClk : in std_logic;
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SDLC_SClk : in std_logic;
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| Line 104... |
Line 101... |
architecture behave of o8_sdlc_if is
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architecture behave of o8_sdlc_if is
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|
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constant Base_Addr : std_logic_vector(15 downto 9)
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constant Base_Addr : std_logic_vector(15 downto 9)
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:= Address(15 downto 9);
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:= Address(15 downto 9);
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|
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alias CPU_Upper_Addr is Bus_Address(15 downto 9);
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alias CPU_Upper_Addr is Open8_Bus.Address(15 downto 9);
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signal Base_Addr_Match : std_logic := '0';
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signal Base_Addr_Match : std_logic := '0';
|
|
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alias DP_A_Addr is Bus_Address(8 downto 0);
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alias DP_A_Addr is Open8_Bus.Address(8 downto 0);
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signal DP_A_Wr_En : std_logic := '0';
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signal DP_A_Wr_En : std_logic := '0';
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alias DP_A_Wr_Data is Wr_Data;
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alias DP_A_Wr_Data is Open8_Bus.Wr_Data;
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signal DP_A_Rd_En : std_logic := '0';
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signal DP_A_Rd_En : std_logic := '0';
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signal DP_A_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
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signal DP_A_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
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|
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constant Reg_Sub_Addr : std_logic_vector(8 downto 1) := x"7F";
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constant Reg_Sub_Addr : std_logic_vector(8 downto 1) := x"7F";
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alias Reg_Upper_Addr is Bus_Address(8 downto 1);
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alias Reg_Upper_Addr is Open8_Bus.Address(8 downto 1);
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alias Reg_Lower_Addr is Bus_Address(0);
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alias Reg_Lower_Addr is Open8_Bus.Address(0);
|
|
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signal Reg_Addr : std_logic_vector(8 downto 1) := (others => '0');
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signal Reg_Addr : std_logic_vector(8 downto 1) := (others => '0');
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signal Reg_Sel : std_logic := '0';
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signal Reg_Sel : std_logic := '0';
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signal Reg_Wr_En : std_logic := '0';
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signal Reg_Wr_En : std_logic := '0';
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signal Reg_Clk_Sel : std_logic := '0';
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signal Reg_Clk_Sel : std_logic := '0';
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| Line 182... |
Line 179... |
-- ***************************************************************************
|
-- ***************************************************************************
|
|
|
-- This decode needs to happen immediately, to give the RAM a chance to
|
-- This decode needs to happen immediately, to give the RAM a chance to
|
-- do the lookup before we have to set Rd_Data
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-- do the lookup before we have to set Rd_Data
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Base_Addr_Match <= '1' when Base_Addr = CPU_Upper_Addr else '0';
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Base_Addr_Match <= '1' when Base_Addr = CPU_Upper_Addr else '0';
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DP_A_Wr_En <= Base_Addr_Match and Wr_Enable;
|
DP_A_Wr_En <= Base_Addr_Match and Open8_Bus.Wr_En;
|
|
|
CPU_IF_proc: process( Reset, Clock )
|
CPU_IF_proc: process( Reset, Clock )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Reg_Addr <= (others => '0');
|
Reg_Addr <= (others => '0');
|
| Line 197... |
Line 194... |
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Interrupt <= '0';
|
Interrupt <= '0';
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
Reg_Addr <= Reg_Upper_Addr;
|
Reg_Addr <= Reg_Upper_Addr;
|
Reg_Sel <= Reg_Lower_Addr;
|
Reg_Sel <= Reg_Lower_Addr;
|
Reg_Wr_En <= Base_Addr_Match and Wr_Enable;
|
Reg_Wr_En <= Base_Addr_Match and Open8_Bus.Wr_En;
|
|
|
Reg_Clk_Sel <= '0';
|
Reg_Clk_Sel <= '0';
|
Reg_TxS_Sel <= '0';
|
Reg_TxS_Sel <= '0';
|
if( Reg_Addr = Reg_Sub_Addr )then
|
if( Reg_Addr = Reg_Sub_Addr )then
|
Reg_Clk_Sel <= Reg_Wr_En and not Reg_Sel;
|
Reg_Clk_Sel <= Reg_Wr_En and not Reg_Sel;
|
Reg_TxS_Sel <= Reg_Wr_En and Reg_Sel;
|
Reg_TxS_Sel <= Reg_Wr_En and Reg_Sel;
|
end if;
|
end if;
|
|
|
DP_A_Rd_En <= Base_Addr_Match and Rd_Enable;
|
DP_A_Rd_En <= Base_Addr_Match and Open8_Bus.Rd_En;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
if( DP_A_Rd_En = '1' )then
|
if( DP_A_Rd_En = '1' )then
|
Rd_Data <= DP_A_Rd_Data;
|
Rd_Data <= DP_A_Rd_Data;
|
end if;
|
end if;
|
|
|
