| Line 57... |
Line 57... |
-- **** This location serves as the status register for the receive
|
-- **** This location serves as the status register for the receive
|
-- 1) This value is only updated on reception of a full frame, indicated
|
-- 1) This value is only updated on reception of a full frame, indicated
|
-- by a start followed by a stop flag. Incomplete frames are ignored.
|
-- by a start followed by a stop flag. Incomplete frames are ignored.
|
-- 2) If too many bytes are received (buffer overflow), a value of
|
-- 2) If too many bytes are received (buffer overflow), a value of
|
-- ERR_LENGTH is written.
|
-- ERR_LENGTH is written.
|
|
--
|
|
-- Revision History
|
|
-- Author Date Change
|
|
------------------ -------- ---------------------------------------------------
|
|
-- Seth Henry 04/16/20 Revision block added
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
| Line 76... |
Line 81... |
Monitor_Enable : boolean := false;
|
Monitor_Enable : boolean := false;
|
Attach_Monitor_to_CPU_Side : boolean := false;
|
Attach_Monitor_to_CPU_Side : boolean := false;
|
Poly_Init : std_logic_vector(15 downto 0) := x"0000";
|
Poly_Init : std_logic_vector(15 downto 0) := x"0000";
|
Set_As_Master : boolean := true;
|
Set_As_Master : boolean := true;
|
Clock_Offset : integer := 6;
|
Clock_Offset : integer := 6;
|
BitClock_Freq : real := 500000.0;
|
BitClock_Frequency : real := 500000.0;
|
Sys_Freq : real := 100000000.0;
|
Clock_Frequency : real := 100000000.0;
|
Reset_Level : std_logic := '1';
|
|
Address : ADDRESS_TYPE
|
Address : ADDRESS_TYPE
|
);
|
);
|
port(
|
port(
|
Clock : in std_logic;
|
|
Reset : in std_logic;
|
|
--
|
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Rd_Data : out DATA_TYPE;
|
Rd_Data : out DATA_TYPE;
|
Interrupt : out std_logic;
|
Interrupt : out std_logic;
|
-- Serial IO
|
-- Serial IO
|
SDLC_In : in std_logic;
|
SDLC_In : in std_logic;
|
| Line 98... |
Line 99... |
);
|
);
|
end entity;
|
end entity;
|
|
|
architecture behave of o8_sdlc_if is
|
architecture behave of o8_sdlc_if is
|
|
|
|
alias Clock is Open8_Bus.Clock;
|
|
alias Reset is Open8_Bus.Reset;
|
|
|
constant Base_Addr : std_logic_vector(15 downto 9)
|
constant Base_Addr : std_logic_vector(15 downto 9)
|
:= Address(15 downto 9);
|
:= Address(15 downto 9);
|
|
|
alias CPU_Upper_Addr is Open8_Bus.Address(15 downto 9);
|
alias CPU_Upper_Addr is Open8_Bus.Address(15 downto 9);
|
signal Base_Addr_Match : std_logic := '0';
|
signal Base_Addr_Match : std_logic := '0';
|
| Line 294... |
Line 298... |
-- ***************************************************************************
|
-- ***************************************************************************
|
|
|
U_BCLK : entity work.sdlc_serial_clk
|
U_BCLK : entity work.sdlc_serial_clk
|
generic map(
|
generic map(
|
Set_As_Master => Set_As_Master,
|
Set_As_Master => Set_As_Master,
|
BitClock_Freq => BitClock_Freq,
|
BitClock_Freq => BitClock_Frequency,
|
Reset_Level => Reset_Level,
|
Reset_Level => Reset_Level,
|
Sys_Freq => Sys_Freq
|
Sys_Freq => Clock_Frequency
|
)
|
)
|
port map(
|
port map(
|
Clock => Clock,
|
Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
--
|
--
|
