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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sdlc_if.vhd] - Diff between revs 244 and 250
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| Rev 244 |
Rev 250 |
| Line 77... |
Line 77... |
library work;
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library work;
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use work.sdlc_serial_pkg.all;
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use work.sdlc_serial_pkg.all;
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entity o8_sdlc_if is
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entity o8_sdlc_if is
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generic(
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generic(
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Monitor_Enable : boolean := false;
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Attach_Monitor_to_CPU_Side : boolean := false;
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Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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Set_As_Master : boolean := true;
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Set_As_Master : boolean := true;
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Clock_Offset : integer := 6;
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Clock_Offset : integer := 6;
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BitClock_Frequency : real := 500000.0;
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BitClock_Frequency : real := 500000.0;
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Clock_Frequency : real := 100000000.0;
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Clock_Frequency : real := 100000000.0;
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| Line 246... |
Line 244... |
wren_b => DP_B_Wr_En,
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wren_b => DP_B_Wr_En,
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q_a => DP_A_Rd_Data,
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q_a => DP_A_Rd_Data,
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q_b => DP_B_Rd_Data
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q_b => DP_B_Rd_Data
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);
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);
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Attach_to_CPU_side: if( Monitor_Enable and Attach_Monitor_to_CPU_Side )generate
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U_MON: entity work.sdlc_monitor
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port map(
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clock => Clock,
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address => DP_A_Addr,
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data => DP_A_Wr_Data,
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wren => DP_A_Wr_En,
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q => open
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);
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end generate;
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Attach_to_Int_side: if( Monitor_Enable and not Attach_Monitor_to_CPU_Side )generate
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U_MON: entity work.sdlc_monitor
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port map(
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clock => Clock,
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address => DP_B_Addr,
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data => DP_B_Wr_Data,
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wren => DP_B_Wr_En,
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q => open
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);
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end generate;
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-- ***************************************************************************
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-- ***************************************************************************
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-- * Memory Arbitration *
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-- * Memory Arbitration *
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-- ***************************************************************************
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-- ***************************************************************************
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U_ARB : entity work.sdlc_serial_arbfsm
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U_ARB : entity work.sdlc_serial_arbfsm
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