| Line 88... |
Line 88... |
);
|
);
|
port(
|
port(
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Write_Qual : in std_logic := '1';
|
Write_Qual : in std_logic := '1';
|
Rd_Data : out DATA_TYPE;
|
Rd_Data : out DATA_TYPE;
|
Interrupt : out std_logic;
|
TX_Interrupt : out std_logic;
|
|
RX_Interrupt : out std_logic;
|
-- Serial IO
|
-- Serial IO
|
SDLC_In : in std_logic;
|
SDLC_In : in std_logic;
|
SDLC_SClk : in std_logic;
|
SDLC_SClk : in std_logic;
|
SDLC_MClk : out std_logic;
|
SDLC_MClk : out std_logic;
|
SDLC_Out : out std_logic
|
SDLC_Out : out std_logic
|
| Line 159... |
Line 160... |
signal TX_CRC_Clr : std_logic := '0';
|
signal TX_CRC_Clr : std_logic := '0';
|
signal TX_CRC_En : std_logic := '0';
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signal TX_CRC_En : std_logic := '0';
|
signal TX_CRC_Data : CRC_OUT_TYPE := x"0000";
|
signal TX_CRC_Data : CRC_OUT_TYPE := x"0000";
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signal TX_CRC_Valid : std_logic := '0';
|
signal TX_CRC_Valid : std_logic := '0';
|
|
|
signal TX_Interrupt : std_logic := '0';
|
|
|
|
signal RX_Valid : std_logic := '0';
|
signal RX_Valid : std_logic := '0';
|
signal RX_Flag : std_logic := '0';
|
signal RX_Flag : std_logic := '0';
|
signal RX_Data : DATA_IN_TYPE;
|
signal RX_Data : DATA_IN_TYPE;
|
signal RX_Idle : std_logic := '0';
|
signal RX_Idle : std_logic := '0';
|
|
|
| Line 174... |
Line 173... |
signal RX_Frame_Data : DATA_IN_TYPE := x"00";
|
signal RX_Frame_Data : DATA_IN_TYPE := x"00";
|
|
|
signal RX_CRC_Valid : std_logic := '0';
|
signal RX_CRC_Valid : std_logic := '0';
|
signal RX_CRC_Data : CRC_OUT_TYPE := x"0000";
|
signal RX_CRC_Data : CRC_OUT_TYPE := x"0000";
|
|
|
signal RX_Interrupt : std_logic := '0';
|
|
|
|
begin
|
begin
|
|
|
-- ***************************************************************************
|
-- ***************************************************************************
|
-- * Open8 Bus Interface and Control Register Detection *
|
-- * Open8 Bus Interface and Control Register Detection *
|
-- ***************************************************************************
|
-- ***************************************************************************
|
| Line 204... |
Line 201... |
Reg_Wr_En_q <= '0';
|
Reg_Wr_En_q <= '0';
|
Reg_Clk_Sel <= '0';
|
Reg_Clk_Sel <= '0';
|
Reg_TxS_Sel <= '0';
|
Reg_TxS_Sel <= '0';
|
DP_A_Rd_En_q <= '0';
|
DP_A_Rd_En_q <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Interrupt <= '0';
|
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
Reg_Addr <= Reg_Upper_Addr;
|
Reg_Addr <= Reg_Upper_Addr;
|
Reg_Sel <= Reg_Lower_Addr;
|
Reg_Sel <= Reg_Lower_Addr;
|
Reg_Wr_En_q <= Reg_Wr_En_d;
|
Reg_Wr_En_q <= Reg_Wr_En_d;
|
|
|
| Line 222... |
Line 218... |
DP_A_Rd_En_q <= DP_A_Rd_En_d;
|
DP_A_Rd_En_q <= DP_A_Rd_En_d;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
if( DP_A_Rd_En_q = '1' )then
|
if( DP_A_Rd_En_q = '1' )then
|
Rd_Data <= DP_A_Rd_Data;
|
Rd_Data <= DP_A_Rd_Data;
|
end if;
|
end if;
|
|
|
Interrupt <= RX_Interrupt or TX_Interrupt;
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- ***************************************************************************
|
-- ***************************************************************************
|
-- * Shared Dual-Port Memory *
|
-- * Shared Dual-Port Memory *
|
