Subversion Repositories open8_urisc

-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF

-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF

-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--

--

-- VHDL Units :  o8_sdlc_if

-- VHDL Units :  o8_sdlc_if

-- Description:  Provides a full memory-mapped SDLC stack with automatic CRC16

-- Description:  Provides a full memory-mapped SDLC stack with automatic CRC16

--

--

-- Transmit Memory Map

-- Transmit Memory Map

-- "0_0000_0000" (0x000) TX Buffer START

-- "0_0000_0000" (0x000) TX Buffer START

-- "0_1111_1101" (0x0FD) TX Buffer END

-- "0_1111_1101" (0x0FD) TX Buffer END

-- "0_1111_1110" (0x0FE) Clock Status*

-- "0_1111_1110" (0x0FE) Clock Status*

-- Revision History

-- Revision History

-- Author          Date     Change

-- Author          Date     Change

------------------ -------- ---------------------------------------------------

------------------ -------- ---------------------------------------------------

-- Seth Henry      04/16/20 Revision block added

-- Seth Henry      04/16/20 Revision block added

-- Seth Henry      05/18/20 Added write qualification input

-- Seth Henry      05/18/20 Added write qualification input

library ieee;

library ieee;

  use ieee.std_logic_1164.all;

  use ieee.std_logic_1164.all;

  use ieee.std_logic_unsigned.all;

  use ieee.std_logic_unsigned.all;

  use ieee.std_logic_arith.all;

  use ieee.std_logic_arith.all;