| Line 130... |
Line 130... |
signal Reg_Wr_En_q : std_logic := '0';
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signal Reg_Wr_En_q : std_logic := '0';
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signal TX_Ctl_Clk : std_logic := '0';
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signal TX_Ctl_Clk : std_logic := '0';
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signal TX_Ctl_Len : std_logic := '0';
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signal TX_Ctl_Len : std_logic := '0';
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-- Dual-port memory
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-- Dual-port memory
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signal DP_Addr : std_logic_vector(8 downto 0);
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signal DP_B_Addr : std_logic_vector(8 downto 0);
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signal DP_Wr_Data : DATA_TYPE;
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signal DP_B_Wr_Data : DATA_TYPE;
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signal DP_Wr_En : std_logic;
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signal DP_B_Wr_En : std_logic;
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signal DP_Rd_Data : DATA_TYPE;
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signal DP_B_Rd_Data : DATA_TYPE;
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alias DP_B_Addr is DP_Addr;
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alias DP_B_Wr_Data is DP_Wr_Data;
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alias DP_B_Wr_En is DP_Wr_En;
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alias DP_B_Rd_Data is DP_Rd_Data;
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-- Internal definitions
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-- Internal definitions
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constant SDLC_Flag : DATA_TYPE := x"7E";
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constant SDLC_Flag : DATA_TYPE := x"7E";
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constant CK_REGISTER : DATA_TYPE := x"FE";
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constant CK_REGISTER : DATA_TYPE := x"FE";
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| Line 394... |
Line 389... |
RAM_Arbitration_proc: process( Clock, Reset )
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RAM_Arbitration_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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DP_Arb_State <= IDLE;
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DP_Arb_State <= IDLE;
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DP_Last_Port <= '0';
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DP_Last_Port <= '0';
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DP_Addr <= (others => '0');
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DP_B_Addr <= (others => '0');
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DP_Wr_Data <= x"00";
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DP_B_Wr_Data <= x"00";
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DP_Wr_En <= '0';
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DP_B_Wr_En <= '0';
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DP_Port0_RdData <= x"00";
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DP_Port0_RdData <= x"00";
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DP_Port0_Ack <= '0';
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DP_Port0_Ack <= '0';
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DP_Port1_RdData <= x"00";
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DP_Port1_RdData <= x"00";
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DP_Port1_Ack <= '0';
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DP_Port1_Ack <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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DP_Port0_Ack <= '0';
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DP_Port0_Ack <= '0';
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DP_Port1_Ack <= '0';
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DP_Port1_Ack <= '0';
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DP_Wr_En <= '0';
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DP_B_Wr_En <= '0';
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case( DP_Arb_State )is
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case( DP_Arb_State )is
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when IDLE =>
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when IDLE =>
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if( DP_Port0_Req = '1' and (DP_Port1_Req = '0' or DP_Last_Port = '1') )then
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if( DP_Port0_Req = '1' and (DP_Port1_Req = '0' or DP_Last_Port = '1') )then
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DP_Arb_State <= PORT0_AD;
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DP_Arb_State <= PORT0_AD;
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| Line 416... |
Line 411... |
DP_Arb_State <= PORT1_AD;
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DP_Arb_State <= PORT1_AD;
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end if;
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end if;
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when PORT0_AD =>
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when PORT0_AD =>
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DP_Last_Port <= '0';
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DP_Last_Port <= '0';
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DP_Addr <= '0' & DP_Port0_Addr;
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DP_B_Addr <= '0' & DP_Port0_Addr;
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DP_Wr_Data <= DP_Port0_WrData;
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DP_B_Wr_Data <= DP_Port0_WrData;
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DP_Wr_En <= not DP_Port0_RWn;
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DP_B_Wr_En <= not DP_Port0_RWn;
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if( DP_Port0_RWn = '1' )then
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if( DP_Port0_RWn = '1' )then
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DP_Arb_State <= PORT0_RD0;
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DP_Arb_State <= PORT0_RD0;
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else
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else
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DP_Port0_Ack <= '1';
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DP_Port0_Ack <= '1';
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DP_Arb_State <= PORT0_WR;
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DP_Arb_State <= PORT0_WR;
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| Line 434... |
Line 429... |
when PORT0_RD0 =>
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when PORT0_RD0 =>
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DP_Arb_State <= PORT0_RD1;
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DP_Arb_State <= PORT0_RD1;
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when PORT0_RD1 =>
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when PORT0_RD1 =>
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DP_Port0_Ack <= '1';
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DP_Port0_Ack <= '1';
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DP_Port0_RdData <= DP_Rd_Data;
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DP_Port0_RdData <= DP_B_Rd_Data;
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DP_Arb_State <= PAUSE;
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DP_Arb_State <= PAUSE;
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when PORT1_AD =>
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when PORT1_AD =>
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DP_Last_Port <= '1';
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DP_Last_Port <= '1';
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DP_Addr <= '1' & DP_Port1_Addr;
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DP_B_Addr <= '1' & DP_Port1_Addr;
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DP_Wr_Data <= DP_Port1_WrData;
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DP_B_Wr_Data <= DP_Port1_WrData;
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DP_Wr_En <= not DP_Port1_RWn;
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DP_B_Wr_En <= not DP_Port1_RWn;
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if( DP_Port0_RWn = '1' )then
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if( DP_Port0_RWn = '1' )then
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DP_Arb_State <= PORT1_RD0;
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DP_Arb_State <= PORT1_RD0;
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else
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else
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DP_Port1_Ack <= '1';
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DP_Port1_Ack <= '1';
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DP_Arb_State <= PORT1_WR;
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DP_Arb_State <= PORT1_WR;
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| Line 457... |
Line 452... |
when PORT1_RD0 =>
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when PORT1_RD0 =>
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DP_Arb_State <= PORT1_RD1;
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DP_Arb_State <= PORT1_RD1;
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when PORT1_RD1 =>
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when PORT1_RD1 =>
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DP_Port1_Ack <= '1';
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DP_Port1_Ack <= '1';
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DP_Port1_RdData <= DP_Rd_Data;
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DP_Port1_RdData <= DP_B_Rd_Data;
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DP_Arb_State <= PAUSE;
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DP_Arb_State <= PAUSE;
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when PAUSE =>
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when PAUSE =>
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DP_Arb_State <= IDLE;
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DP_Arb_State <= IDLE;
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