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signal Reg_Wr_En_q : std_logic := '0';
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signal Reg_Wr_En_q : std_logic := '0';
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signal TX_Ctl_Clk : std_logic := '0';
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signal TX_Ctl_Clk : std_logic := '0';
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signal TX_Ctl_Len : std_logic := '0';
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signal TX_Ctl_Len : std_logic := '0';
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-- Dual-port memory
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-- Dual-port memory
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signal DP_B_Addr : std_logic_vector(8 downto 0);
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signal DP_B_Addr : std_logic_vector(8 downto 0) := (others => '0');
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signal DP_B_Wr_Data : DATA_TYPE;
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signal DP_B_Wr_Data : DATA_TYPE := x"00";
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signal DP_B_Wr_En : std_logic;
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signal DP_B_Wr_En : std_logic := '0';
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signal DP_B_Rd_Data : DATA_TYPE;
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signal DP_B_Rd_Data : DATA_TYPE := x"00";
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-- Internal definitions
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-- Internal definitions
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constant SDLC_Flag : DATA_TYPE := x"7E";
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constant SDLC_Flag : DATA_TYPE := x"7E";
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constant CK_REGISTER : DATA_TYPE := x"FE";
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constant CK_REGISTER : DATA_TYPE := x"FE";
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Line 183... |
signal BClk_Adv : std_logic := '0';
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signal BClk_Adv : std_logic := '0';
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signal BClk_Accum : std_logic_vector(31 downto 0) := (others => '0');
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signal BClk_Accum : std_logic_vector(31 downto 0) := (others => '0');
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signal BClk_Div : std_logic := '0';
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signal BClk_Div : std_logic := '0';
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signal BClk_Okay_SR : std_logic_vector(3 downto 0) := (others => '0');
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signal BClk_Okay_SR : std_logic_vector(3 downto 0) := (others => '0');
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signal BClk_SR : std_logic_vector(2 downto 0) := (others => '0');
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signal BClk_SR : std_logic_vector(2 downto 0) := (others => '0');
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constant CLK_RATIO_R : real := Clock_Frequency / (1.0 * BitClock_Frequency);
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constant CLK_RATIO_R : real := Clock_Frequency / (1.0 * BitClock_Frequency);
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constant CLK_DEVIATION_5P : real := CLK_RATIO_R * 0.05;
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constant CLK_DEVIATION_5P : real := CLK_RATIO_R * 0.05;
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constant CLK_RATIO_ADJ_R : real := CLK_RATIO_R + CLK_DEVIATION_5P;
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constant CLK_RATIO_ADJ_R : real := CLK_RATIO_R + CLK_DEVIATION_5P;
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