| Line 216... |
Line 216... |
WR_CLOCK_STATE, WAIT_FOR_CLOCK,
|
WR_CLOCK_STATE, WAIT_FOR_CLOCK,
|
WAIT_FOR_UPDATE,
|
WAIT_FOR_UPDATE,
|
RD_TX_REGISTER, TX_INIT,
|
RD_TX_REGISTER, TX_INIT,
|
TX_START_FLAG, TX_WAIT_START_FLAG,
|
TX_START_FLAG, TX_WAIT_START_FLAG,
|
TX_MESG_DATA, TX_ADV_ADDR, TX_WAIT_MESG_DATA,
|
TX_MESG_DATA, TX_ADV_ADDR, TX_WAIT_MESG_DATA,
|
TX_CRC_LB_WR, TX_CRC_LB_WAIT,
|
TX_CRC_LB_WR, TX_WAIT_CRC_LB,
|
TX_CRC_UB_WR, TX_CRC_UB_WAIT,
|
TX_CRC_UB_WR, TX_WAIT_CRC_UB,
|
TX_STOP_FLAG, TX_WAIT_STOP_FLAG, TX_SET_FLAG );
|
TX_STOP_FLAG, TX_WAIT_STOP_FLAG, TX_SET_FLAG );
|
|
|
signal TX_FSM_State : TX_FSM_STATES := WR_CLOCK_STATE;
|
signal TX_FSM_State : TX_FSM_STATES := WR_CLOCK_STATE;
|
signal TX_Length : DATA_TYPE := x"00";
|
signal TX_Length : DATA_TYPE := x"00";
|
|
|
| Line 694... |
Line 694... |
end if;
|
end if;
|
|
|
when TX_CRC_LB_WR =>
|
when TX_CRC_LB_WR =>
|
TX_Wr_En <= '1';
|
TX_Wr_En <= '1';
|
TX_Wr_Data <= TX_CRC_Data_LB;
|
TX_Wr_Data <= TX_CRC_Data_LB;
|
TX_FSM_State <= TX_CRC_LB_WAIT;
|
TX_FSM_State <= TX_WAIT_CRC_LB;
|
|
|
when TX_CRC_LB_WAIT =>
|
when TX_WAIT_CRC_LB =>
|
if( TX_Req_Next = '1' )then
|
if( TX_Req_Next = '1' )then
|
TX_FSM_State <= TX_CRC_UB_WR;
|
TX_FSM_State <= TX_CRC_UB_WR;
|
end if;
|
end if;
|
|
|
when TX_CRC_UB_WR =>
|
when TX_CRC_UB_WR =>
|
TX_Wr_En <= '1';
|
TX_Wr_En <= '1';
|
TX_Wr_Data <= TX_CRC_Data_UB;
|
TX_Wr_Data <= TX_CRC_Data_UB;
|
TX_FSM_State <= TX_CRC_UB_WAIT;
|
TX_FSM_State <= TX_WAIT_CRC_UB;
|
|
|
when TX_CRC_UB_WAIT =>
|
when TX_WAIT_CRC_UB =>
|
if( TX_Req_Next = '1' )then
|
if( TX_Req_Next = '1' )then
|
TX_FSM_State <= TX_STOP_FLAG;
|
TX_FSM_State <= TX_STOP_FLAG;
|
end if;
|
end if;
|
|
|
when TX_STOP_FLAG =>
|
when TX_STOP_FLAG =>
|
