| Line 210... |
Line 210... |
signal BClk_RE : std_logic := '0';
|
signal BClk_RE : std_logic := '0';
|
signal BClk_FE : std_logic := '0';
|
signal BClk_FE : std_logic := '0';
|
signal BClk_Okay : std_logic := '0';
|
signal BClk_Okay : std_logic := '0';
|
|
|
-- Packet Transmit state logic
|
-- Packet Transmit state logic
|
type TX_FSM_STATES is ( INIT_FLAG,
|
type TX_FSM_STATES is ( INIT_FLAG, WR_CLOCK_STATE, WAIT_FOR_UPDATE,
|
WR_CLOCK_STATE, WAIT_FOR_CLOCK,
|
|
WAIT_FOR_UPDATE,
|
|
RD_TX_REGISTER, TX_INIT,
|
RD_TX_REGISTER, TX_INIT,
|
TX_START_FLAG, TX_WAIT_START_FLAG,
|
TX_START_FLAG, TX_WAIT_START_FLAG,
|
TX_MESG_DATA, TX_ADV_ADDR, TX_WAIT_MESG_DATA,
|
TX_MESG_DATA, TX_ADV_ADDR, TX_WAIT_MESG_DATA,
|
TX_CRC_LB_WR, TX_WAIT_CRC_LB,
|
TX_CRC_LB_WR, TX_WAIT_CRC_LB,
|
TX_CRC_UB_WR, TX_WAIT_CRC_UB,
|
TX_CRC_UB_WR, TX_WAIT_CRC_UB,
|
| Line 614... |
Line 612... |
if( DP_Port0_Ack = '1' )then
|
if( DP_Port0_Ack = '1' )then
|
DP_Port0_Req <= '0';
|
DP_Port0_Req <= '0';
|
TX_FSM_State <= WR_CLOCK_STATE;
|
TX_FSM_State <= WR_CLOCK_STATE;
|
end if;
|
end if;
|
|
|
when WAIT_FOR_UPDATE =>
|
|
if( TX_Ctl_Clk = '1' )then
|
|
TX_FSM_State <= WR_CLOCK_STATE;
|
|
end if;
|
|
if( TX_Ctl_Len = '1' )then
|
|
TX_FSM_State <= RD_TX_REGISTER;
|
|
end if;
|
|
|
|
when WR_CLOCK_STATE =>
|
when WR_CLOCK_STATE =>
|
DP_Port0_Addr <= CK_REGISTER;
|
DP_Port0_Addr <= CK_REGISTER;
|
DP_Port0_Req <= '1';
|
DP_Port0_Req <= '1';
|
DP_Port0_WrData <= (others => BClk_Okay);
|
DP_Port0_WrData <= (others => BClk_Okay);
|
DP_Port0_RWn <= '0';
|
DP_Port0_RWn <= '0';
|
if( DP_Port0_Ack = '1' )then
|
if( DP_Port0_Ack = '1' )then
|
TX_Interrupt <= TX_Int_pend;
|
TX_Interrupt <= TX_Int_pend;
|
TX_Int_pend <= '0';
|
TX_Int_pend <= '0';
|
DP_Port0_Req <= '0';
|
DP_Port0_Req <= '0';
|
TX_FSM_State <= WAIT_FOR_CLOCK;
|
TX_FSM_State <= WAIT_FOR_UPDATE;
|
end if;
|
end if;
|
|
|
when WAIT_FOR_CLOCK =>
|
when WAIT_FOR_UPDATE =>
|
if( BClk_Okay = '1' )then
|
if( TX_Ctl_Clk = '1' )then
|
TX_FSM_State <= WAIT_FOR_UPDATE;
|
TX_FSM_State <= WR_CLOCK_STATE;
|
|
end if;
|
|
if( TX_Ctl_Len = '1' and BClk_Okay = '1' )then
|
|
TX_FSM_State <= RD_TX_REGISTER;
|
end if;
|
end if;
|
|
|
when RD_TX_REGISTER =>
|
when RD_TX_REGISTER =>
|
DP_Port0_Addr <= TX_REGISTER;
|
DP_Port0_Addr <= TX_REGISTER;
|
DP_Port0_Req <= '1';
|
DP_Port0_Req <= '1';
|
