| Line 56... |
Line 56... |
);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Bus_Address : in ADDRESS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
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Wr_Enable : in std_logic;
|
|
Wr_Data : in DATA_TYPE;
|
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Rd_Enable : in std_logic;
|
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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LED_Out : out std_logic
|
LED_Out : out std_logic
|
);
|
);
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end entity;
|
end entity;
|
|
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architecture behave of o8_status_led is
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architecture behave of o8_status_led is
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|
|
constant User_Addr : std_logic_vector(15 downto 0)
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constant User_Addr : std_logic_vector(15 downto 0)
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:= Address(15 downto 0);
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:= Address(15 downto 0);
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alias Comp_Addr is Bus_Address(15 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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signal Wr_En : std_logic;
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signal Wr_En : std_logic;
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signal Wr_Data_q : std_logic_vector(2 downto 0);
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signal Wr_Data_q : std_logic_vector(2 downto 0);
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signal LED_Mode : std_logic_vector(2 downto 0);
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signal LED_Mode : std_logic_vector(2 downto 0);
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signal Rd_En : std_logic;
|
signal Rd_En : std_logic;
|
| Line 103... |
Line 100... |
Wr_Data_q <= (others => '0');
|
Wr_Data_q <= (others => '0');
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LED_Mode <= (others => '0');
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LED_Mode <= (others => '0');
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Rd_En <= '0';
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Rd_En <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
|
Wr_Data_q <= Wr_Data(2 downto 0);
|
Wr_Data_q <= Open8_Bus.Wr_Data(2 downto 0);
|
if( Wr_En = '1' )then
|
if( Wr_En = '1' )then
|
LED_Mode <= Wr_Data_q;
|
LED_Mode <= Wr_Data_q;
|
end if;
|
end if;
|
|
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Addr_Match and Rd_Enable;
|
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
|
if( Rd_En = '1' )then
|
if( Rd_En = '1' )then
|
Rd_Data <= "00000" & LED_Mode;
|
Rd_Data <= "00000" & LED_Mode;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
