| Line 38... |
Line 38... |
-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 12/20/19 Design Start
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-- Seth Henry 12/20/19 Design Start
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 05/18/20 Added write qualification input
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 54... |
Line 55... |
generic(
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generic(
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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LED_Out : out std_logic
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LED_Out : out std_logic
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);
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);
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end entity;
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end entity;
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| Line 69... |
Line 71... |
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constant User_Addr : std_logic_vector(15 downto 0)
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constant User_Addr : std_logic_vector(15 downto 0)
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:= Address(15 downto 0);
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:= Address(15 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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signal Wr_En : std_logic;
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signal Wr_Data_q : std_logic_vector(2 downto 0);
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal LED_Mode : std_logic_vector(2 downto 0);
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signal LED_Mode : std_logic_vector(2 downto 0);
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signal Rd_En : std_logic;
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signal Dim50Pct_Out : std_logic;
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signal Dim50Pct_Out : std_logic;
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|
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signal Half_Hz_Timer : std_logic_vector(15 downto 0);
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signal Half_Hz_Timer : std_logic_vector(15 downto 0);
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constant HALF_HZ_PRD : std_logic_vector(15 downto 0) :=
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constant HALF_HZ_PRD : std_logic_vector(15 downto 0) :=
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| Line 90... |
Line 97... |
signal Fade_Out : std_logic;
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signal Fade_Out : std_logic;
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begin
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begin
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|
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Wr_En <= '0';
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Wr_En_q <= '0';
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Wr_Data_q <= (others => '0');
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Wr_Data_q <= x"00";
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LED_Mode <= (others => '0');
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Rd_En_q <= '0';
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Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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LED_Mode <= (others => '0');
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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Wr_En_q <= Wr_En_d;
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Wr_Data_q <= Open8_Bus.Wr_Data(2 downto 0);
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Wr_Data_q <= Wr_Data_d;
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if( Wr_En = '1' )then
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if( Wr_En_q = '1' and Write_Qual = '1' )then
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LED_Mode <= Wr_Data_q;
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LED_Mode <= Wr_Data_q(2 downto 0);
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end if;
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end if;
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Rd_En_q <= Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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if( Rd_En_q = '1' )then
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if( Rd_En = '1' )then
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Rd_Data <= "00000" & LED_Mode;
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Rd_Data <= "00000" & LED_Mode;
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end if;
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end if;
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|
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end if;
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end if;
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end process;
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end process;
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