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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_status_led.vhd] - Diff between revs 244 and 249
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| Rev 244 |
Rev 249 |
| Line 124... |
Line 124... |
end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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Output_FF: process( Clock, Reset )
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U_LED_DRV : entity work.status_led
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begin
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generic map(
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if( Reset = Reset_Level )then
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Reset_Level => Reset_Level
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LED_Out <= '0';
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)
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elsif( rising_edge(Clock) )then
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port map(
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LED_Out <= '0';
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Clock => Clock,
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case( LED_Mode )is
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Reset => Reset,
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when "001" =>
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LED_Mode => LED_Mode,
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LED_Out <= '1';
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LED_Out => LED_Out
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when "010" =>
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);
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LED_Out <= Dim50Pct_Out;
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when "011" =>
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LED_Out <= One_Hz_Out;
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when "100" =>
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LED_Out <= Fade_out;
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when others => null;
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end case;
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end if;
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end process;
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Timer_proc: process( Clock, Reset )
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begin
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if( Reset = Reset_Level )then
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Dim50Pct_Out <= '0';
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Half_Hz_Timer <= (others => '0');
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One_Hz_Out <= '0';
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Fade_Timer1 <= (others => '0');
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Fade_Timer2 <= (others => '0');
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Fade_out <= '0';
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elsif( rising_edge(Clock) )then
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Dim50Pct_Out <= not Dim50Pct_Out;
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Half_Hz_Timer <= Half_Hz_Timer - 1;
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if( Half_Hz_Timer = 0 )then
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Half_Hz_Timer <= HALF_HZ_PRD;
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One_Hz_Out <= not One_Hz_Out;
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end if;
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Fade_Timer1 <= Fade_Timer1 - 1;
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Fade_Timer2 <= Fade_Timer2 - 1;
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if( or_reduce(Fade_Timer2) = '0' )then
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Fade_Timer2(TIMER_MSB downto TIMER_MSB - 8) <= (others => '1');
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Fade_Timer2(TIMER_MSB - 9 downto 0 ) <= (others => '0');
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end if;
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Fade_out <= Fade_Timer1(TIMER_MSB) xor
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Fade_Timer2(TIMER_MSB);
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end if;
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end process;
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end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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