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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sys_timer.vhd] - Diff between revs 184 and 189
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| Rev 184 |
Rev 189 |
| Line 76... |
Line 76... |
signal Rd_En_q : std_logic;
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signal Rd_En_q : std_logic;
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signal Interval : DATA_TYPE;
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signal Interval : DATA_TYPE;
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signal Timer_Cnt : DATA_TYPE;
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signal Timer_Cnt : DATA_TYPE;
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-- The ceil_log2 function returns the minimum register width required to
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-- hold the supplied integer.
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function ceil_log2 (x : in natural) return natural is
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variable retval : natural;
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begin
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retval := 1;
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while ((2**retval) - 1) < x loop
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retval := retval + 1;
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end loop;
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return retval;
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end ceil_log2;
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constant DLY_1USEC_VAL: integer := integer(Sys_Freq / 1000000.0);
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constant DLY_1USEC_VAL: integer := integer(Sys_Freq / 1000000.0);
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constant DLY_1USEC_WDT: integer := ceil_log2(DLY_1USEC_VAL - 1);
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constant DLY_1USEC_WDT: integer := ceil_log2(DLY_1USEC_VAL - 1);
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constant DLY_1USEC : std_logic_vector :=
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constant DLY_1USEC : std_logic_vector :=
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conv_std_logic_vector(DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
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conv_std_logic_vector(DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
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