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Line 67... |
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architecture behave of o8_sys_timer is
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architecture behave of o8_sys_timer is
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constant User_Addr : ADDRESS_TYPE := Address;
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constant User_Addr : ADDRESS_TYPE := Address;
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alias Comp_Addr is Bus_Address(15 downto 0);
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alias Comp_Addr is Bus_Address(15 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic := '0';
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signal Wr_En : std_logic;
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signal Wr_En : std_logic := '0';
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signal Wr_Data_q : DATA_TYPE;
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signal Wr_Data_q : DATA_TYPE := OPEN8_NULLBUS;
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signal Rd_En : std_logic;
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signal Rd_En : std_logic := '0';
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signal Rd_En_q : std_logic;
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signal Rd_En_q : std_logic := '0';
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signal Interval : DATA_TYPE;
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signal Interval : DATA_TYPE := x"00";
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signal Timer_Cnt : DATA_TYPE;
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signal Timer_Cnt : DATA_TYPE := x"00";
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constant DLY_1USEC_VAL: integer := integer(Sys_Freq / 1000000.0);
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constant DLY_1USEC_VAL: integer := integer(Sys_Freq / 1000000.0);
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constant DLY_1USEC_WDT: integer := ceil_log2(DLY_1USEC_VAL - 1);
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constant DLY_1USEC_WDT: integer := ceil_log2(DLY_1USEC_VAL - 1);
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constant DLY_1USEC : std_logic_vector :=
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constant DLY_1USEC : std_logic_vector :=
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conv_std_logic_vector(DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
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conv_std_logic_vector(DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
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signal uSec_Cntr : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )
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signal uSec_Cntr : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )
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:= (others => '0');
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:= (others => '0');
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signal uSec_Tick_i : std_logic;
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signal uSec_Tick_i : std_logic := '0';
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begin
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begin
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uSec_Tick <= uSec_Tick_i;
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uSec_Tick <= uSec_Tick_i;
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Line 95... |
begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Wr_En <= '0';
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Wr_En <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= x"00";
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Rd_Data <= OPEN8_NULLBUS;
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Interval <= x"00";
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Interval <= x"00";
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_Data_q <= Wr_Data;
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Wr_Data_q <= Wr_Data;
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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