| Line 33... |
Line 33... |
-- Revision History
|
-- Revision History
|
-- Author Date Change
|
-- Author Date Change
|
------------------ -------- ---------------------------------------------------
|
------------------ -------- ---------------------------------------------------
|
-- Seth Henry 07/28/11 Design Start
|
-- Seth Henry 07/28/11 Design Start
|
-- Seth Henry 12/19/19 Renamed Tmr_Out to Interrupt
|
-- Seth Henry 12/19/19 Renamed Tmr_Out to Interrupt
|
|
-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
|
|
-- interval write.
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
| Line 74... |
Line 76... |
signal Wr_Data_q : DATA_TYPE := OPEN8_NULLBUS;
|
signal Wr_Data_q : DATA_TYPE := OPEN8_NULLBUS;
|
signal Rd_En : std_logic := '0';
|
signal Rd_En : std_logic := '0';
|
signal Rd_En_q : std_logic := '0';
|
signal Rd_En_q : std_logic := '0';
|
|
|
signal Interval : DATA_TYPE := x"00";
|
signal Interval : DATA_TYPE := x"00";
|
|
signal Update_Interval : std_logic;
|
|
signal New_Interval : DATA_TYPE := x"00";
|
signal Timer_Cnt : DATA_TYPE := x"00";
|
signal Timer_Cnt : DATA_TYPE := x"00";
|
|
|
constant DLY_1USEC_VAL: integer := integer(Sys_Freq / 1000000.0);
|
constant DLY_1USEC_VAL: integer := integer(Sys_Freq / 1000000.0);
|
constant DLY_1USEC_WDT: integer := ceil_log2(DLY_1USEC_VAL - 1);
|
constant DLY_1USEC_WDT: integer := ceil_log2(DLY_1USEC_VAL - 1);
|
constant DLY_1USEC : std_logic_vector :=
|
constant DLY_1USEC : std_logic_vector :=
|
| Line 97... |
Line 101... |
Wr_En <= '0';
|
Wr_En <= '0';
|
Wr_Data_q <= x"00";
|
Wr_Data_q <= x"00";
|
Rd_En <= '0';
|
Rd_En <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Interval <= x"00";
|
Interval <= x"00";
|
|
Update_Interval <= '0';
|
|
New_Interval <= x"00";
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_Data_q <= Wr_Data;
|
Wr_Data_q <= Wr_Data;
|
|
Update_Interval <= '0';
|
if( Wr_En = '1' )then
|
if( Wr_En = '1' )then
|
Interval <= Wr_Data_q;
|
New_Interval <= Wr_Data_q;
|
|
Update_Interval <= '1';
|
end if;
|
end if;
|
|
|
Rd_Data <= (others => '0');
|
Rd_Data <= (others => '0');
|
Rd_En <= Addr_Match and Rd_Enable;
|
Rd_En <= Addr_Match and Rd_Enable;
|
if( Rd_En = '1' )then
|
if( Rd_En = '1' )then
|
