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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sys_timer.vhd] - Diff between revs 211 and 223

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Rev 211 Rev 223
Line 56... Line 56...
port(
port(
  Clock                      : in  std_logic;
  Clock                      : in  std_logic;
  Reset                      : in  std_logic;
  Reset                      : in  std_logic;
  uSec_Tick                  : out std_logic;
  uSec_Tick                  : out std_logic;
  --
  --
  Bus_Address                : in  ADDRESS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Wr_Enable                  : in  std_logic;
 
  Wr_Data                    : in  DATA_TYPE;
 
  Rd_Enable                  : in  std_logic;
 
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
  Interrupt                  : out std_logic
  Interrupt                  : out std_logic
);
);
end entity;
end entity;
 
 
architecture behave of o8_sys_timer is
architecture behave of o8_sys_timer is
 
 
  constant User_Addr         : ADDRESS_TYPE := Address;
  constant User_Addr         : ADDRESS_TYPE := Address;
  alias  Comp_Addr           is Bus_Address(15 downto 0);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
  signal Addr_Match          : std_logic := '0';
  signal Addr_Match          : std_logic := '0';
  signal Wr_En               : std_logic := '0';
  signal Wr_En               : std_logic := '0';
  signal Wr_Data_q           : DATA_TYPE := OPEN8_NULLBUS;
  signal Wr_Data_q           : DATA_TYPE := x"00";
  signal Rd_En               : std_logic := '0';
  signal Rd_En               : std_logic := '0';
  signal Rd_En_q             : std_logic := '0';
  signal Rd_En_q             : std_logic := '0';
 
 
  signal Interval            : DATA_TYPE := x"00";
  signal Interval            : DATA_TYPE := x"00";
  signal Update_Interval     : std_logic;
  signal Update_Interval     : std_logic;
Line 102... Line 99...
      Rd_En                  <= '0';
      Rd_En                  <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      Interval               <= x"00";
      Interval               <= x"00";
      Update_Interval        <= '0';
      Update_Interval        <= '0';
    elsif( rising_edge( Clock ) )then
    elsif( rising_edge( Clock ) )then
      Wr_En                  <= Addr_Match and Wr_Enable;
      Wr_En                  <= Addr_Match and Open8_Bus.Wr_En;
      Wr_Data_q              <= Wr_Data;
      Wr_Data_q              <= Open8_Bus.Wr_Data;
      Update_Interval        <= '0';
      Update_Interval        <= '0';
      if( Wr_En = '1' )then
      if( Wr_En = '1' )then
        Interval             <= Wr_Data_q;
        Interval             <= Wr_Data_q;
        Update_Interval      <= '1';
        Update_Interval      <= '1';
      end if;
      end if;
 
 
      Rd_Data                <= (others => '0');
      Rd_Data                <= (others => '0');
      Rd_En                  <= Addr_Match and Rd_Enable;
      Rd_En                  <= Addr_Match and Open8_Bus.Rd_En;
      if( Rd_En = '1' )then
      if( Rd_En = '1' )then
        Rd_Data              <= Interval;
        Rd_Data              <= Interval;
      end if;
      end if;
    end if;
    end if;
  end process;
  end process;

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