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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sys_timer.vhd] - Diff between revs 223 and 224

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Rev 223 Rev 224
Line 35... Line 35...
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      07/28/11 Design Start
-- Seth Henry      07/28/11 Design Start
-- Seth Henry      12/19/19 Renamed Tmr_Out to Interrupt
-- Seth Henry      12/19/19 Renamed Tmr_Out to Interrupt
-- Seth Henry      04/09/20 Modified timer update logic to reset the timer on
-- Seth Henry      04/09/20 Modified timer update logic to reset the timer on
--                           interval write.
--                           interval write.
 
-- Seth Henry      04/16/20 Modified to use Open8 bus record
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_arith.all;
Line 47... Line 48...
library work;
library work;
  use work.open8_pkg.all;
  use work.open8_pkg.all;
 
 
entity o8_sys_timer is
entity o8_sys_timer is
generic(
generic(
  Sys_Freq                   : real;
 
  Reset_Level                : std_logic;
 
  Address                    : ADDRESS_TYPE
  Address                    : ADDRESS_TYPE
);
);
port(
port(
  Clock                      : in  std_logic;
 
  Reset                      : in  std_logic;
 
  uSec_Tick                  : out std_logic;
 
  --
 
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
  Interrupt                  : out std_logic
  Interrupt                  : out std_logic
);
);
end entity;
end entity;
 
 
architecture behave of o8_sys_timer is
architecture behave of o8_sys_timer is
 
 
 
  alias Clock                is Open8_Bus.Clock;
 
  alias Reset                is Open8_Bus.Reset;
 
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
 
 
  constant User_Addr         : ADDRESS_TYPE := Address;
  constant User_Addr         : ADDRESS_TYPE := Address;
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
  signal Addr_Match          : std_logic := '0';
  signal Addr_Match          : std_logic := '0';
  signal Wr_En               : std_logic := '0';
  signal Wr_En               : std_logic := '0';
  signal Wr_Data_q           : DATA_TYPE := x"00";
  signal Wr_Data_q           : DATA_TYPE := x"00";
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  signal Interval            : DATA_TYPE := x"00";
  signal Interval            : DATA_TYPE := x"00";
  signal Update_Interval     : std_logic;
  signal Update_Interval     : std_logic;
  signal Timer_Cnt           : DATA_TYPE := x"00";
  signal Timer_Cnt           : DATA_TYPE := x"00";
 
 
  constant DLY_1USEC_VAL     : integer := integer(Sys_Freq / 1000000.0);
 
  constant DLY_1USEC_WDT     : integer := ceil_log2(DLY_1USEC_VAL - 1);
 
  constant DLY_1USEC         : std_logic_vector :=
 
                      conv_std_logic_vector(DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
 
 
 
  signal uSec_Cntr           : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )
 
                               := (others => '0');
 
  signal uSec_Tick_i         : std_logic := '0';
 
begin
begin
 
 
  uSec_Tick                  <= uSec_Tick_i;
 
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
 
 
  io_reg: process( Clock, Reset )
  io_reg: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
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        Rd_Data              <= Interval;
        Rd_Data              <= Interval;
      end if;
      end if;
    end if;
    end if;
  end process;
  end process;
 
 
  uSec_Tick_i_proc: process( Clock, Reset )
 
  begin
 
    if( Reset = Reset_Level )then
 
      uSec_Cntr              <= (others => '0');
 
      uSec_Tick_i            <= '0';
 
    elsif( rising_edge( Clock ) )then
 
      uSec_Cntr              <= uSec_Cntr - 1;
 
      uSec_Tick_i            <= '0';
 
      if( uSec_Cntr = 0 )then
 
        uSec_Cntr            <= DLY_1USEC;
 
        uSec_Tick_i          <= '1';
 
      end if;
 
    end if;
 
  end process;
 
 
 
  Interval_proc: process( Clock, Reset )
  Interval_proc: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Timer_Cnt              <= x"00";
      Timer_Cnt              <= x"00";
      Interrupt              <= '0';
      Interrupt              <= '0';
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      Interrupt              <= '0';
      Interrupt              <= '0';
      Timer_Cnt              <= Timer_Cnt - uSec_Tick_i;
      Timer_Cnt              <= Timer_Cnt - uSec_Tick;
      if( Update_Interval = '1' )then
      if( Update_Interval = '1' )then
        Timer_Cnt            <= Interval;
        Timer_Cnt            <= Interval;
      elsif( or_reduce(Timer_Cnt) = '0' )then
      elsif( or_reduce(Timer_Cnt) = '0' )then
        Timer_Cnt            <= Interval;
        Timer_Cnt            <= Interval;
        Interrupt            <= or_reduce(Interval); -- Only trigger on Int > 0
        Interrupt            <= or_reduce(Interval); -- Only trigger on Int > 0

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