| Line 35... |
Line 35... |
------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 12/19/19 Renamed Tmr_Out to Interrupt
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-- Seth Henry 12/19/19 Renamed Tmr_Out to Interrupt
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-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
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-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
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-- interval write.
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-- interval write.
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 47... |
Line 48... |
library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_sys_timer is
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entity o8_sys_timer is
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generic(
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generic(
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Sys_Freq : real;
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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uSec_Tick : out std_logic;
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--
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic
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Interrupt : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_sys_timer is
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architecture behave of o8_sys_timer is
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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constant User_Addr : ADDRESS_TYPE := Address;
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constant User_Addr : ADDRESS_TYPE := Address;
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Wr_En : std_logic := '0';
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signal Wr_En : std_logic := '0';
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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| Line 76... |
Line 75... |
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signal Interval : DATA_TYPE := x"00";
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signal Interval : DATA_TYPE := x"00";
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signal Update_Interval : std_logic;
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signal Update_Interval : std_logic;
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signal Timer_Cnt : DATA_TYPE := x"00";
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signal Timer_Cnt : DATA_TYPE := x"00";
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constant DLY_1USEC_VAL : integer := integer(Sys_Freq / 1000000.0);
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constant DLY_1USEC_WDT : integer := ceil_log2(DLY_1USEC_VAL - 1);
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constant DLY_1USEC : std_logic_vector :=
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conv_std_logic_vector(DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
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signal uSec_Cntr : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )
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:= (others => '0');
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signal uSec_Tick_i : std_logic := '0';
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begin
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begin
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uSec_Tick <= uSec_Tick_i;
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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| Line 115... |
Line 105... |
Rd_Data <= Interval;
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Rd_Data <= Interval;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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uSec_Tick_i_proc: process( Clock, Reset )
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begin
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if( Reset = Reset_Level )then
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uSec_Cntr <= (others => '0');
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uSec_Tick_i <= '0';
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elsif( rising_edge( Clock ) )then
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uSec_Cntr <= uSec_Cntr - 1;
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uSec_Tick_i <= '0';
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if( uSec_Cntr = 0 )then
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uSec_Cntr <= DLY_1USEC;
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uSec_Tick_i <= '1';
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end if;
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end if;
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end process;
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Interval_proc: process( Clock, Reset )
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Interval_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Timer_Cnt <= x"00";
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Timer_Cnt <= x"00";
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Interrupt <= '0';
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Interrupt <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Interrupt <= '0';
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Interrupt <= '0';
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Timer_Cnt <= Timer_Cnt - uSec_Tick_i;
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Timer_Cnt <= Timer_Cnt - uSec_Tick;
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if( Update_Interval = '1' )then
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if( Update_Interval = '1' )then
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Timer_Cnt <= Interval;
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Timer_Cnt <= Interval;
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elsif( or_reduce(Timer_Cnt) = '0' )then
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elsif( or_reduce(Timer_Cnt) = '0' )then
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Timer_Cnt <= Interval;
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Timer_Cnt <= Interval;
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Interrupt <= or_reduce(Interval); -- Only trigger on Int > 0
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Interrupt <= or_reduce(Interval); -- Only trigger on Int > 0
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