URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sys_timer.vhd] - Diff between revs 224 and 229
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 224 |
Rev 229 |
| Line 23... |
Line 23... |
--
|
--
|
-- VHDL Units : o8_sys_timer
|
-- VHDL Units : o8_sys_timer
|
-- Description: Provides an 8-bit microsecond resolution timer for generating
|
-- Description: Provides an 8-bit microsecond resolution timer for generating
|
-- : periodic interrupts for the Open8 CPU.
|
-- : periodic interrupts for the Open8 CPU.
|
--
|
--
|
-- Notes : It is possible to set the value to zero, resulting in the
|
-- Notes : Setting the output to 0x00 will disable the timer
|
-- : output staying high indefinitely. This may cause an issue if
|
|
-- : the output is connected to an interrupt input.
|
|
-- : Also provides uSec_Tick as an output
|
|
--
|
--
|
-- Revision History
|
-- Revision History
|
-- Author Date Change
|
-- Author Date Change
|
------------------ -------- ---------------------------------------------------
|
------------------ -------- ---------------------------------------------------
|
-- Seth Henry 07/28/11 Design Start
|
-- Seth Henry 07/28/11 Design Start
|
| Line 97... |
Line 94... |
if( Wr_En = '1' )then
|
if( Wr_En = '1' )then
|
Interval <= Wr_Data_q;
|
Interval <= Wr_Data_q;
|
Update_Interval <= '1';
|
Update_Interval <= '1';
|
end if;
|
end if;
|
|
|
Rd_Data <= (others => '0');
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
|
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
|
if( Rd_En = '1' )then
|
if( Rd_En = '1' )then
|
Rd_Data <= Interval;
|
Rd_Data <= Interval;
|
end if;
|
end if;
|
end if;
|
end if;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.