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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sys_timer.vhd] - Diff between revs 229 and 242

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Line 23... Line 23...
--
--
-- VHDL Units :  o8_sys_timer
-- VHDL Units :  o8_sys_timer
-- Description:  Provides an 8-bit microsecond resolution timer for generating
-- Description:  Provides an 8-bit microsecond resolution timer for generating
--            :   periodic interrupts for the Open8 CPU.
--            :   periodic interrupts for the Open8 CPU.
--
--
-- Notes      :  Setting the output to 0x00 will disable the timer
-- Notes      :  It is possible to set the value to zero, resulting in the
 
--            :   output staying high indefinitely. This may cause an issue if
 
--            :   the output is connected to an interrupt input.
 
--            :  Also provides uSec_Tick as an output
--
--
-- Revision History
-- Revision History
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      07/28/11 Design Start
-- Seth Henry      07/28/11 Design Start
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library work;
library work;
  use work.open8_pkg.all;
  use work.open8_pkg.all;
 
 
entity o8_sys_timer is
entity o8_sys_timer is
generic(
generic(
 
  Write_Protect              : boolean := FALSE;
  Address                    : ADDRESS_TYPE
  Address                    : ADDRESS_TYPE
);
);
port(
port(
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
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architecture behave of o8_sys_timer is
architecture behave of o8_sys_timer is
 
 
  alias Clock                is Open8_Bus.Clock;
  alias Clock                is Open8_Bus.Clock;
  alias Reset                is Open8_Bus.Reset;
  alias Reset                is Open8_Bus.Reset;
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
 
  alias ISR_En               is Open8_Bus.GP_Flags(EXT_ISR);
 
 
 
  signal Wr_En_d             : std_logic;
 
  signal Rd_En_d             : std_logic;
 
 
 
  alias Wr_Data              is Open8_Bus.Wr_Data;
 
 
  constant User_Addr         : ADDRESS_TYPE := Address;
  constant User_Addr         : ADDRESS_TYPE := Address;
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
  signal Addr_Match          : std_logic := '0';
  signal Addr_Match          : std_logic := '0';
  signal Wr_En               : std_logic := '0';
  signal Wr_En               : std_logic := '0';
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begin
begin
 
 
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
 
 
 
  -- If the Write_Protect generic is set only allow the memory to be written
 
  --  if the ISR bit is set. Otherwise, the memory should be read-only
 
 
 
Write_Protect_On : if( Write_Protect )generate
 
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En and ISR_En;
 
end generate;
 
 
 
Write_Protect_Off : if( not Write_Protect )generate
 
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En;
 
end generate;
 
 
 
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
 
 
  io_reg: process( Clock, Reset )
  io_reg: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Wr_En                  <= '0';
      Wr_En                  <= '0';
      Wr_Data_q              <= x"00";
      Wr_Data_q              <= x"00";
      Rd_En                  <= '0';
      Rd_En                  <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      Interval               <= x"00";
      Interval               <= x"00";
      Update_Interval        <= '0';
      Update_Interval        <= '0';
    elsif( rising_edge( Clock ) )then
    elsif( rising_edge( Clock ) )then
      Wr_En                  <= Addr_Match and Open8_Bus.Wr_En;
      Wr_En                  <= Wr_En_d;
      Wr_Data_q              <= Open8_Bus.Wr_Data;
      Wr_Data_q              <= Wr_Data;
      Update_Interval        <= '0';
 
 
      Update_Interval        <= Wr_En;
      if( Wr_En = '1' )then
      if( Wr_En = '1' )then
        Interval             <= Wr_Data_q;
        Interval             <= Wr_Data_q;
        Update_Interval      <= '1';
 
      end if;
      end if;
 
 
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= (others => '0');
      Rd_En                  <= Addr_Match and Open8_Bus.Rd_En;
      Rd_En                  <= Rd_En_d;
      if( Rd_En = '1' )then
      if( Rd_En = '1' )then
        Rd_Data              <= Interval;
        Rd_Data              <= Interval;
      end if;
      end if;
    end if;
    end if;
  end process;
  end process;

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