| Line 23... |
Line 23... |
--
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--
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-- VHDL Units : o8_sys_timer
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-- VHDL Units : o8_sys_timer
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-- Description: Provides an 8-bit microsecond resolution timer for generating
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-- Description: Provides an 8-bit microsecond resolution timer for generating
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-- : periodic interrupts for the Open8 CPU.
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-- : periodic interrupts for the Open8 CPU.
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--
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--
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-- Notes : It is possible to set the value to zero, resulting in the
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-- : output staying high indefinitely. This may cause an issue if
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-- : the output is connected to an interrupt input.
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-- : Also provides uSec_Tick as an output
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 07/28/11 Design Start
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_sys_timer is
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entity o8_sys_timer is
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generic(
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generic(
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mSec_Resolution : boolean := FALSE;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Write_Qual : in std_logic := '1';
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Line 77... |
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signal Interval : DATA_TYPE := x"00";
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signal Interval : DATA_TYPE := x"00";
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signal Update_Interval : std_logic;
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signal Update_Interval : std_logic;
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signal Timer_Cnt : DATA_TYPE := x"00";
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signal Timer_Cnt : DATA_TYPE := x"00";
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constant MSEC_DELAY : std_logic_vector(9 downto 0) :=
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conv_std_logic_vector(1000,10);
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signal mSec_Timer : std_logic_vector(9 downto 0) := (others => '0');
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signal Timer_Tick : std_logic := '0';
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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mSec_Resolution_enabled : if( mSec_Resolution )generate
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mSec_Tick_proc: process( Clock, Reset )
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begin
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if( Reset = Reset_Level )then
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mSec_Timer <= (others => '0');
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Timer_Tick <= '0';
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elsif( rising_edge(Clock) )then
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mSec_Timer <= mSec_Timer - uSec_Tick;
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Timer_Tick <= '0';
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if( mSec_Timer = 0 )then
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mSec_Timer <= MSEC_DELAY;
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Timer_Tick <= '1';
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end if;
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end if;
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end process;
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end generate;
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uSec_Resolution_enabled : if( not mSec_Resolution )generate
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Timer_Tick <= uSec_Tick;
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end generate;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Wr_En_q <= '0';
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Wr_En_q <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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Line 148... |
if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Timer_Cnt <= x"00";
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Timer_Cnt <= x"00";
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Interrupt <= '0';
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Interrupt <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Interrupt <= '0';
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Interrupt <= '0';
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Timer_Cnt <= Timer_Cnt - uSec_Tick;
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Timer_Cnt <= Timer_Cnt - Timer_Tick;
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if( Update_Interval = '1' )then
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if( Update_Interval = '1' )then
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Timer_Cnt <= Interval;
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Timer_Cnt <= Interval;
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elsif( or_reduce(Timer_Cnt) = '0' )then
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elsif( or_reduce(Timer_Cnt) = '0' )then
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Timer_Cnt <= Interval;
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Timer_Cnt <= Interval;
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Interrupt <= or_reduce(Interval); -- Only trigger on Int > 0
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Interrupt <= or_reduce(Interval); -- Only trigger on Int > 0
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