| Line 20... |
Line 20... |
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_sys_timer
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-- VHDL Units : o8_sys_timer
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-- Description: Provides an 8-bit microsecond resolution timer for generating
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-- Description: Provides an 8-bit milli/microsecond resolution timer for
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-- : periodic interrupts for the Open8 CPU.
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-- : generating periodic interrupts for the Open8 CPU.
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--
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--
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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| Line 33... |
Line 33... |
-- Seth Henry 12/19/19 Renamed Tmr_Out to Interrupt
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-- Seth Henry 12/19/19 Renamed Tmr_Out to Interrupt
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-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
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-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
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-- interval write.
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-- interval write.
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 05/18/20 Added write qualification input
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-- Seth Henry 05/18/20 Added write qualification input
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-- Seth Henry 11/01/20 Changed description to note different resolutions
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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