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Line 75... |
architecture behave of o8_sys_timer_ii is
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architecture behave of o8_sys_timer_ii is
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias CPU_Wr_En is Open8_Bus.Wr_En
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alias CPU_Rd_En is Open8_Bus.Rd_En
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constant User_Addr : std_logic_vector(15 downto 2) :=
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constant User_Addr : std_logic_vector(15 downto 2) :=
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Address(15 downto 2);
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Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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Line 114... |
signal Timer_Tick : std_logic := '0';
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signal Timer_Tick : std_logic := '0';
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
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Wr_En_d <= Addr_Match and Write_Qual and CPU_Wr_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_d <= Addr_Match and CPU_Rd_En;
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mSec_Resolution_enabled : if( mSec_Resolution )generate
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mSec_Resolution_enabled : if( mSec_Resolution )generate
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mSec_Tick_proc: process( Clock, Reset )
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mSec_Tick_proc: process( Clock, Reset )
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begin
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begin
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Reg_Sel_q <= Reg_Sel_d;
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Reg_Sel_q <= Reg_Sel_d;
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Wr_En_q <= Wr_En_d;
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Wr_En_q <= Wr_En_d;
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Wr_Data_q <= Wr_Data_d;
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Wr_Data_q <= Wr_Data_d;
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Update_Interval <= '0';
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Update_Interval <= '0';
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if( Wr_En_q = '1' and Write_Qual = '1' )then
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if( Wr_En_q = '1' )then
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case( Reg_Sel_q )is
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case( Reg_Sel_q )is
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when "00" =>
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when "00" =>
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Req_Interval_B0 <= Wr_Data_q;
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Req_Interval_B0 <= Wr_Data_q;
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Update_Pending <= '1';
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Update_Pending <= '1';
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when "01" =>
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when "01" =>
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