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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_trig_delay.vhd] - Diff between revs 244 and 274

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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
--
 
--
 
-- VHDL Entity: o8_trig_delay
 
-- VHDL Entity: o8_trig_delay
 
-- Description: Receives a 6-bit vector command and 16-bit argument from the
 
-- Description: Programmable delay timer with time-base selection. Allows both
 
--               vector_tx entity. Issues interrupt to the CPU on receipt of
 
--               they delay after triggering and pulse width to be set by
 
--               three bytes.
 
--               software. Output may either be routed to a pin or used to
 
 
 
--               trigger an interrupt.
 
--
 
--
 
-- Register Map:
 
-- Register Map:
 
-- Offset  Bitfield Description                        Read/Write
 
-- Offset  Bitfield Description                        Read/Write
 
--   0x0   AAAAAAAA Delay Time  Byte 0                     (RW)
 
--   0x0   AAAAAAAA Delay Time  Byte 0                     (RW)
 
--   0x1   AAAAAAAA Delay Time  Byte 1                     (RW)
 
--   0x1   AAAAAAAA Delay Time  Byte 1                     (RW)

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